An Adaptive Timing-Driven Layout for High Speed VLSI. - Suphachai Sutanthavibul; Eugene Shragowitz (DAC, 1990)

Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. - Suphachai Sutanthavibul; Eugene Shragowitz (DAC, 1991)

An analytical approach to floorplan design and optimization. - Suphachai Sutanthavibul; Eugene Shragowitz; J. Ben Rosen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Prelayout timing analysis of cell-based VLSI designs. - Habib Youssef; Eugene Shragowitz; Suphachai Sutanthavibul (Comput. Aided Des., 1992)

An adaptive timing-driven placement for high performance VLSIs. - Suphachai Sutanthavibul; Eugene Shragowitz; Rung-Bin Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Net criticality revisited: an effective method to improve timing in physical design. - H. Chang; Eugene Shragowitz; Jian Liu; Habib Youssef; Bing Lu; Suphachai Sutanthavibul (ISPD, 2002)