Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (Asian Test Symposium, 2009)

Polynomial coefficient based DC testing of non-linear analog circuits. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (ACM Great Lakes Symposium on VLSI, 2009)

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (VLSI Design, 2010)

Test and Diagnosis of Analog Circuits Using Moment Generating Functions. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (Asian Test Symposium, 2011)

Testing linear and non-linear analog circuits using moment generating functions. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (LATW, 2011)

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (VTS, 2011)

Tailoring Tests for Functional Binning of Integrated Circuits. - Suraj Sindia; Vishwani D. Agrawal (Asian Test Symposium, 2012)

Impact of process variations on computers used for image processing. - Suraj Sindia; Fa Foster Dai; Vishwani D. Agrawal; Virendra Singh (ISCAS, 2012)

Towards spatial fault resilience in array processors. - Suraj Sindia; Vishwani D. Agrawal (VTS, 2012)

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (J. Electron. Test., 2012)

Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (J. Electron. Test., 2012)

High sensitivity test signatures for unconventional analog circuit test paradigms. - Suraj Sindia; Vishwani D. Agrawal (ITC, 2013)

Finding best voltage and frequency to shorten power-constrained test time. - Praveen Venkataramani; Suraj Sindia; Vishwani D. Agrawal (VTS, 2013)

Neural Network Guided Spatial Fault Resilience in Array Processors. - Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2013)

Specification test minimization for given defect level. - Suraj Sindia; Vishwani D. Agrawal (LATW, 2014)

A Test Time Theorem and its Applications. - Praveen Venkataramani; Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2014)

Innovative practices session 2C: New technologies, new challenges - 2. - Suraj Sindia (VTS, 2015)

Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. - Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2015)