SRAM based longest prefix matching approach for multigigabit IP processing. - Sanchita Saha Ray; Surajeet Ghosh; Bhaskar Sardar (IEEE ANTS, 2015)

An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup. - Sanchita Saha Ray; Surajeet Ghosh; Bhaskar Sardar (Photonic Netw. Commun., 2016)

A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing. - Sanchita Saha Ray; Sonal Singh; Chandrayan Sengupta; Surajeet Ghosh; Bhaskar Sardar (ANTS, 2018)

A Comparison-free Hardware Sorting Engine. - Surajeet Ghosh; Shaon Dasgupta; Sanchita Saha Ray (ISVLSI, 2019)

Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU. - Ardhendu Sarkar; Kinjal Ray; Debaroti Chowdhury; Kishan Sahu; Solanki Kundu; Surajeet Ghosh (TENCON, 2019)

An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment. - Ardhendu Sarkar; Som Banerjee; Surajeet Ghosh (IEEE Trans. Very Large Scale Integr. Syst., 2020)

CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism. - Surajeet Ghosh; Anirban Chand (ANTS, 2022)

Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing. - Sanchita Saha Ray; Surajeet Ghosh; Bhaskar Sardar (IEEE Trans. Computers, 2022)

Worst Case O(N) Comparison-Free Hardware Sorting Engine. - Sanchita Saha Ray; Dulal Adak; Surajeet Ghosh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting. - Sanchita Saha Ray; Surajeet Ghosh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

${O(N)}$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform. - Surajeet Ghosh; Sanchita Saha Ray (IEEE Trans. Computers, 2023)

Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment. - Ardhendu Sarkar; Surajeet Ghosh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)