IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off. - Surajit Bhattacherjee; Dipankar Pal (ICNC, 2023)

Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape. - Surajit Bhattacherjee; Daksh Shah; Dipankar Pal (AICAS, 2024)