Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. - Surajit Kumar Roy; Chandan Giri; Arnab Chakraborty; Subhro Mukherjee; Debesh K. Das; Hafizur Rahaman 001 (ISED, 2011)

Optimization of Test Wrapper for TSV Based 3D SOCs. - Surajit Kumar Roy; Chandan Giri; Sourav Ghosh; Hafizur Rahaman 001 (ISED, 2011)

Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs. - Surajit Kumar Roy; Chandan Giri; Sourav Ghosh; Hafizur Rahaman 001 (ISVLSI, 2011)

Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing. - Surajit Kumar Roy; Sobitri Chatterjee; Chandan Giri (ISED, 2012)

Testing 3D stacked ICs for post-bond partial/complete stack. - Surajit Kumar Roy; Dona Roy; Chandan Giri; Hafizur Rahman (MWSCAS, 2012)

Post-bond Stack Testing for 3D Stacked IC. - Surajit Kumar Roy; Dona Roy; Chandan Giri; Hafizur Rahaman 001 (VDAT, 2012)

Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. - Surajit Kumar Roy; Sobitri Chatterjee; Chandan Giri; Hafizur Rahaman 001 (3DIC, 2013)

Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs. - Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (IDT, 2013)

Power constraints test scheduling of 3D stacked ICs. - Surajit Kumar Roy; Joy Sankar Sengupta; Chandan Giri; Hafizur Rahaman 001 (IDT, 2013)

Session Based Core Test Scheduling for 3D SOCs. - Surajit Kumar Roy; Payel Ghosh; Hafizur Rahaman 001; Chandan Giri (ISVLSI, 2014)

Test Time Optimization for 3D-SICs Having Multiple Towers. - Sumit Dhuwalia; Nikhil Khemka; Prince Gupta; Surajit Kumar Roy; Chandan Giri (iNIS, 2015)

Recovery of faulty TSVs in 3D ICs. - Surajit Kumar Roy; Kaustav Roy; Chandan Giri; Hafizur Rahaman 001 (ISQED, 2015)

A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. - Surajit Kumar Roy; Supriyo Mandal; Chandan Giri; Hafizur Rahaman 001 (VLSI-SoC, 2015)

Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. - Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2015)

Optimization of Test Wrapper for TSV Based 3D SOCs. - Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (J. Electron. Test., 2016)

TSV repairing for 3D ICs using redundant TSV. - Sudeep Ghosh; Surajit Kumar Roy; Hafizur Rahaman 001; Chandan Giri (ISED, 2017)

Design-for-test and test time optimization for 3D SOCs. - Surajit Kumar Roy; Chandan Giri (ITC, 2017)

Modeling and Analysis of Transient Heat for 3D IC. - Subhajit Chatterjee; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (VDAT, 2017)

Faulty TSVs Identification in 3D IC Using Pre-bond Testing. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri (VDAT, 2017)

Identification of Faulty TSV with a Built-In Self-Test Mechanism. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (ATS, 2018)

Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs. - Tapobrata Dhar; Surajit Kumar Roy; Chandan Giri (VDAT, 2018)

Identification of Faulty TSVs in 3D IC During Pre-Bond Testing. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri (VLSID, 2018)

Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip. - Sourav Ghosh; Dolan Maity; Arijit Chowdhury; Surajit Kumar Roy; Chandan Giri (ATS, 2019)

Hardware Trojan Detection by Stimulating Transitions in Rare Nets. - Tapobrata Dhar; Surajit Kumar Roy; Chandan Giri (VLSID, 2019)

Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri (J. Electron. Test., 2019)

An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs. - Subhajit Chatterjee; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (ISDCS, 2020)

Hardware Trojan Detection Using Improved Testability Measures. - Priyanka Naskar; Tapobrata Dhar; Surajit Kumar Roy (ISDCS, 2020)

Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets. - Sourav Ghosh; Surajit Kumar Roy; Chandan Giri (J. Electron. Test., 2021)

Hardware Trojan Horse Detection through Improved Switching of Dormant Nets. - Tapobrata Dhar; Surajit Kumar Roy; Chandan Giri (ACM J. Emerg. Technol. Comput. Syst., 2021)

TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri (ACM J. Emerg. Technol. Comput. Syst., 2022)

Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation. - Subhajit Chatterjee; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (Microelectron. J., 2022)

Cost Effective Single Target Sample Preparation on Digital Microfluidic Biochip. - Sourav Ghosh; Surajit Kumar Roy; Chandan Giri (iSES, 2023)

Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation. - Sourav Ghosh; Surajit Kumar Roy; Chandan Giri (J. Electron. Test., 2023)

Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection. - Tapobrata Dhar; Ranit Das; Chandan Giri; Surajit Kumar Roy (J. Electron. Test., 2023)

Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri (Integr., 2024)

Localisation of malicious nets in integrated circuits using unsupervised methodologies. - Tapobrata Dhar; Chandan Giri; Surajit Kumar Roy (Integr., 2025)