Experiments with simulated annealing. - Surendra Nahar; Sartaj Sahni; Eugene Shragowitz (DAC, 1985)

A time and space efficient net extractor. - Surendra Nahar; Sartaj Sahni (DAC, 1986)

Simulated annealing and combinatorial optimization. - Surendra Nahar; Sartaj Sahni; Eugene Shragowitz (DAC, 1986)

Fast algorithm for polygon decomposition. - Surendra Nahar; Sartaj K. Sahni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Time-efficient VLSI artwork analysis algorithms in GOALIE2. - Kuang-Wei Chiang; Surendra Nahar; Chi-Yuan Lo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A cell-based hierarchical pitchmatching compaction using minimal LP. - So-Zen Yao; Chung-Kuan Cheng; Debaprosad Dutt; Surendra Nahar; Chi-Yuan Lo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)