Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains. - Suresh Balasubramanian; Narayanan Natarajan; Olivier Franza; Chris Gianos (VLSI Design, 2006)

A 32-core RISC microprocessor with network accelerators, power management and testability features. - Brian Miller; Derek Brasili; Tim Kiszely; Rob Kuhn; Rahul Mehrotra; Manan Salvi; Mandar Kulkarni; Anand Varadharajan; Shi-Huang Yin; William Lin; Adam Hughes; Bill Stysiack; et al. (ISSCC, 2012)