Bounded Queries and the NP Machine Hypothesis. - Richard Chang 001; Suresh Purini (CCC, 2007)

Amplifying ZPP^SAT[1] and the Two Queries Problem. - Richard Chang 001; Suresh Purini (CCC, 2008)

Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting. - Bharghava Rajaram; Abinesh Ramachandran; Suresh Purini; Govindarajulu Regeti (VLSI Design, 2010)

Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer. - Abinesh Ramachandran; Bharghava Rajaram; Suresh Purini; Govindarajulu Regeti (VLSI Design, 2010)

Design of Low Power Systems Using Inexact Logic Circuits. - Bharghava Rajaram; Abinesh Ramachandran; Suresh Purini; R. Govindatajulu (J. Low Power Electron., 2010)

Virtual Machine Coscheduling: A Game Theoretic Approach. - Jaspal Singh Dhillon; Suresh Purini; Sanidhya Kashyap (UCC, 2013)

Finding good optimization sequences covering program space. - Suresh Purini; Lakshya Jain (ACM Trans. Archit. Code Optim., 2013)

RLC - A Reliable Approach to Fast and Efficient Live Migration of Virtual Machines in the Clouds. - Sanidhya Kashyap; Jaspal Singh Dhillon; Suresh Purini (IEEE CLOUD, 2014)

Dynamic Memory and Core Scaling in Virtual Machines. - Kapil Kumar; Nehal J. Wani; Suresh Purini (CLOUD, 2015)

A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. - Nitin Chugh; Vinay Vasista; Suresh Purini; Uday Bondhugula (PACT, 2016)

Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only). - Ronak Kogta; Suresh Purini; Ajit Mathew (FPGA, 2016)

Anuvaad Pranaali: A RESTful API for Machine Translation. - Nehal J. Wani; Sharada Prasanna Mohanty; Suresh Purini; Dipti Misra Sharma (ICSOC Workshops, 2016)

A Hybrid CPU+GPU Working-Set Dictionary. - Ziaul Choudhury; Suresh Purini; Shiva Rama Krishna (ISPDC, 2016)

Distributed Safety Verification Using Vertex Centric Programming Model. - Adhish Singla; Krishnaji Desai; Suresh Purini; Venkatesh Choppella (ISPDC, 2016)

Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits. - Vinamra Benara; Suresh Purini (ISVLSI, 2016)

Fast algorithms for optimal coalition formation in federated clouds. - Yash Khandelwal; Suresh Purini; Puduru V. Reddy (UCC, 2016)

Plagiarism Detection in Programming Assignments Using Deep Features. - Jitendra Yasaswi; Suresh Purini; C. V. Jawahar (ACPR, 2017)

Unsupervised Learning Based Approach for Plagiarism Detection in Programming Assignments. - Jitendra Yasaswi; Sri Kailash; Anil Chilupuri; Suresh Purini; C. V. Jawahar (ISEC, 2017)

Cloud Federation Formation in Oligopolistic Markets. - Yash Khandelwal; Karthik Ganti; Suresh Purini; Puduru V. Reddy (Euro-Par, 2018)

Share-a-GPU: Providing Simple and Effective Time-Sharing on GPUs. - Shaleen Garg; Kishore Kothapalli; Suresh Purini (HiPC, 2018)

Flow Sensor IoT Node for Wi-Fi Equipped Apartments and Gated Communities. - Deepak Awasthi; Syed Azeemuddin; Suresh Purini; Annesha Mazumder (IEEE SENSORS, 2018)

A Multi-Cloud Marketplace Model with Multiple Brokers for IaaS Layer and Generalized Stable Matching. - Shrenik Jain; Suresh Purini; Puduru V. Reddy (UCC, 2018)

Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. - Vinamra Benara; Sahithi Rampalli; Ziaul Choudhury; Suresh Purini; Uday Bondhugula (CoRR, 2018)

Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. - Suresh Purini; Vinamra Benara; Ziaul Choudhury; Uday Bondhugula (CC, 2020)

Accelerating Local Laplacian Filters on FPGAs. - Shashwat Khandelwal; Ziaul Choudhury; Shashwat Shrivastava; Suresh Purini (FPL, 2020)

FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. - Shashwat Shrivastava; Ziaul Choudhury; Shashwat Khandelwal; Suresh Purini (FPL, 2020)

Model Checking as a Service using Dynamic Resource Scaling. - Surya Teja Palavalasa; Yuvraj Singh; Adhish Singla; Suresh Purini; Venkatesh Choppella (HiPC, 2020)

Pricing strategies of an oligopolist in federated cloud markets. - Yash Khandelwal; Arushi Dogra; Karthik Ganti; Suresh Purini; Puduru V. Reddy (J. Cloud Comput., 2021)

Systolic Array based FPGA accelerator for Yolov3-tiny. - Prithvi Velicheti; Sivani Pentapati; Suresh Purini (HPEC, 2022)

Accuracy Configurable FPGA Implementation of Harris Corner Detection. - Shivani Maurya; Ziaul Choudhury; Suresh Purini (ISVLSI, 2022)

An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism. - Ziaul Choudhury; Shashwat Shrivastava; Lavanya Ramapantulu; Suresh Purini (ACM Trans. Archit. Code Optim., 2022)

A Cloud-Fog Architecture for Video Analytics on Large Scale Camera Networks Using Semantic Scene Analysis. - Kunal Jain; Kishan Sairam Adapa; Kunwar Grover; Ravi Kiran Sarvadevabhatla; Suresh Purini (CCGrid, 2023)

Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs. - Vaibhav Kashera; Siddhant Jain; Abhishek Banerjee; Suresh Purini (FPL, 2023)

Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System. - Shaarada D. Yamini; Mirishkar Sai Ganesh; Anil Kumar Vuppala; Suresh Purini (IPDPS Workshops, 2023)

FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler. - Ziaul Choudhury; Anish Gulati; Suresh Purini (ACM Trans. Archit. Code Optim., 2023)

Seer: A Framework for Optimizing Traffic Camera Placement and Deep Learning Inference at the Edge for Vehicle Path Reconstruction. - Siddhant Jain; Kunal Jain; Arun Ravindran; Suresh Purini (SEC, 2024)