Advancing high performance heterogeneous integration through die stacking. - Liam Madden; Ephrem Wu; Namhoon Kim; Bahareh Banijamali; Khaldoon Abugharbieh; Suresh Ramalingam; Xin Wu (ESSCIRC, 2012)

FPGAs with 28Gb/s transceivers built with heterogeneous stacked-silicon interconnects. - Ephrem Wu; Suresh Ramalingam (Hot Chips Symposium, 2012)

Interconnect and package design of a heterogeneous stacked-silicon FPGA. - Ephrem Wu; Khaldoon Abugharbieh; Bahareh Banijamali; Suresh Ramalingam; Paul Wu; Chris Wyland (CICC, 2013)

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. - Kang Wook Lee 002; Ai Nakamura; Jicheol Bea; Takafumi Fukushima; Suresh Ramalingam; Xin Wu; Tanaka Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

HBM package integration: Technology trends, challenges and applications. - Suresh Ramalingam (Hot Chips Symposium, 2016)

CCECE 2021 Invited Paper: Holistic Performance, Reliability and Thermal Understanding of HPC Real Utilization on Silicon Architecture. - Gamal Refai-Ahmed; Hoa Do; I-Ru Chen; Jae-Gyung Ahn; Huayan Wang; Xin Wu; Suresh Ramalingam (CCECE, 2021)

Enabling Chiplet Integration Beyond 7nm (Invited). - Suresh Ramalingam (SLIP, 2021)