Process Variations and their Impact on Circuit Operation. - Suriyaprakash Natarajan; Melvin A. Breuer; Sandeep K. Gupta 001 (DFT, 1998)

Switch-level delay test. - Suriyaprakash Natarajan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 1999)

Switch-level delay test of domino logic circuits. - Suriyaprakash Natarajan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2001)

XIDEN: Crosstalk Target Identification Framework. - Shahin Nazarian; Hang Huang; Suriyaprakash Natarajan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2002)

Untestable Multi-Cycle Path Delay Faults in Industrial Designs. - Manan Syal; Michael S. Hsiao; Suriyaprakash Natarajan; Sreejit Chakravarty (Asian Test Symposium, 2005)

Selecting High-Quality Delay Tests for Manufacturing Test and Debug. - Hangkyu Lee; Suriyaprakash Natarajan; Srinivas Patil; Irith Pomeranz (DFT, 2006)

Path Delay Fault Simulation on Large Industrial Designs. - Suriyaprakash Natarajan; Srinivas Patil; Sreejit Chakravarty (VTS, 2006)

The Region-Exhaustive Fault Model. - Abhijit Jas; Suriyaprakash Natarajan; Srinivas Patil (ATS, 2007)

On efficient generation of instruction sequences to test for delay defects in a processor. - Sankar Gurumurthy; Ramtilak Vemu; Jacob A. Abraham; Suriyaprakash Natarajan (ACM Great Lakes Symposium on VLSI, 2008)

On Accelerating Path Delay Fault Simulation of Long Test Sequences. - I-De Huang; Yi-Shing Chang; Suriyaprakash Natarajan; Ramesh Sharma; Sandeep K. Gupta 001 (ITC, 2008)

Case Study on Speed Failure Causes in a Microprocessor. - Kip Killpack; Suriyaprakash Natarajan; Arun Krishnamachary; Pouria Bastani (IEEE Des. Test Comput., 2008)

Path coverage based functional test generation for processor marginality validation. - Suriyaprakash Natarajan; Arun Krishnamachary; Eli Chiprout; Rajesh Galivanche (ITC, 2010)

Innovative practices session 9C: Implications of power delivery network for validation and testing. - Suriyaprakash Natarajan (VTS, 2010)

The buck stops with wafer test: Dream or reality? - Suriyaprakash Natarajan; Arani Sinha (VTS, 2011)

The bang for the buck with resiliency: Yield or field? - Arani Sinha; Suriyaprakash Natarajan (VTS, 2011)

Scalable and efficient analog parametric fault identification. - Mustafa Berke Yelten; Suriyaprakash Natarajan; Bin Xue; Prashant Goteti (ICCAD, 2013)

Framework for analog test coverage. - Debesh Bhatta; Ishita Mukhopadhyay; Suriyaprakash Natarajan; Prashant Goteti; Bin Xue (ISQED, 2013)

Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity. - Helia Naeimi; Suriya Natarajan; Kushagra Vaid; Prabhakar Kudva; Mahesh Natu (VTS, 2013)

Special session 12B: Panel post-silicon validation & test in huge variance era. - Takahiro J. Yamaguchi; Jacob A. Abraham; Gordon W. Roberts; Suriyaprakash Natarajan; Dennis J. Ciplickas (VTS, 2013)

Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. - Ali Ahmadi; Ke Huang 001; Suriyaprakash Natarajan; John M. Carulli Jr.; Yiorgos Makris (ITC, 2014)

Innovative practices session 4C: Disruptive solutions in the non-digital world. - Amitava Majumdar 002; Suriya Natarajan; Stephen K. Sunter; Prashant Goteti; Ke Huang 001 (VTS, 2014)

Hot topic session 9C: Test and fault tolerance for emerging memory technologies. - Suriya Natarajan; Amitava Majumdar 002; Jeyavijayan Rajendran (VTS, 2014)

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. - Ashwin Chintaluri; Abhinav Parihar; Suriyaprakash Natarajan; Helia Naeimi; Arijit Raychowdhury (ATS, 2015)

Fast eye diagram analysis for high-speed CMOS circuits. - Seyed Nematollah Ahmadyan; Chenjie Gu; Suriyaprakash Natarajan; Eli Chiprout; Shobha Vasudevan (DATE, 2015)

Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. - Chong Li; Suriyaprakash Natarajan; Chuanjin Richard Shi (ICECS, 2015)

Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts? - Sreekumar V. Kodakara; Suriya Natarajan (VTS, 2015)

Innovative practices session 7C: Mixed signal test and debug. - Suriya Natarajan (VTS, 2015)

Every test makes a difference: Compressing analog tests to decrease production costs. - Seyed Nematollah Ahmadyan; Suriyaprakash Natarajan; Shobha Vasudevan (ASP-DAC, 2016)

Fault simulation for analog test coverage. - Jyotsna Sequeira; Suriyaprakash Natarajan; Prashant Goteti; Nitin Chaudhary (ITC, 2016)

Infant mortality tests for analog and mixed-signal circuits. - Suvadeep Banerjee; Suriyaprakash Natarajan (VTS, 2016)

Session 4B - Panel data analytics in semiconductor manufacturing. - Suriyaprakash Natarajan; Li-C. Wang (VTS, 2016)

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. - Ashwin Chintaluri; Helia Naeimi; Suriyaprakash Natarajan; Arijit Raychowdhury (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Innovative practices session 4C data analytics in test. - Suriya Natarajan; Abhijit Sathaye (VTS, 2017)

Innovative practices session 3C hardware security. - Jeyavijayan (JV) Rajendran; Peilin Song; Suriya Natarajan (VTS, 2017)

A novel test compression algorithm for analog circuits to decrease production costs. - Seyed Nematollah Ahmadyan; Suriyaprakash Natarajan; Shobha Vasudevan (Integr., 2017)

Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology. - Sujay Pandey; Sanya Gupta; Madhu Sudhan L.; Suriya Natarajan; Arani Sinha; Abhijit Chatterjee (ITC, 2019)

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. - Sujay Pandey; Zhiwei Liao; Shreyas Nandi; Sanya Gupta; Suriyaprakash Natarajan; Arani Sinha; Adit D. Singh; Abhijit Chatterjee (ITC, 2020)

Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. - Srikanth Venkataraman; Pongpachara Limpisathian; Pascal Meinerzhagen; Suriyaprakash Natarajan; Eric Yang (ITC, 2020)

Automated Design For Yield Through Defect Tolerance. - Suriyaprakash Natarajan; Andres F. Malavasi; Pascal Andreas Meinerzhagen (VTS, 2020)

HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators. - Ayush Arunachalam; Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Suriyaprakash Natarajan; Kanad Basu (ISQED, 2021)

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. - Sujay Pandey; Zhiwei Liao; Shreyas Nandi; Suriyaprakash Natarajan; Arani Sinha; Adit D. Singh; Abhijit Chatterjee (VTS, 2021)

Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ATS, 2022)

A defect tolerance framework for improving yield. - Shiva Shankar Thiagarajan; Suriyaprakash Natarajan; Yiorgos Makris (DAC, 2022)

DEFCON: Defect Acceleration through Content Optimization. - Suriyaprakash Natarajan; Abhijit Sathaye; Chaitali Oak; Nipun Chaplot; Suvadeep Banerjee (ITC, 2022)

Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. - Ayush Arunachalam; Sanjay Das; Monikka Rajan; Fei Su; Xiankun Jin; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu (ITC, 2023)

Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators. - Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Suriyaprakash Natarajan; Kanad Basu (IEEE Des. Test, 2023)

A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators. - Ayush Arunachalam; Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Fei Su; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Computers, 2023)

Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. - Sanjay Das; Shamik Kundu; Pooja Madhusoodhanan; Viswanathan Pillai Prasanth; Rubin A. Parekhji; Arnab Raha; Suvadeep Banerjee; Suriya Natarajan; Kanad Basu (DAC, 2024)

Generating Storage-Aware Test Sets Targeting Several Fault Models. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ISVLSI, 2024)

TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering. - Suhasini Komarraju; Mohamed Mejri; Abhijit Chatterjee; Suriyaprakash Natarajan; Prashant Goteti (ITC, 2024)

Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor. - Suriyaprakash Natarajan; Chaitali S. Oak; Vijay Kakollu; Nipun Chaplot; Soham Roy; Apurva Lonkar; Gerardo J. Perfecto Reyes (ITC, 2024)

Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors. - Suhas Krishna Kashyap; Chinmaye Raghavendra; Suriyaprakash Natarajan; Sule Ozev (VTS, 2024)

Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. - Ayush Arunachalam; Ian Kintz; Suvadeep Banerjee; Arnab Raha; Xiankun Jin; Fei Su; Viswanathan Pillai Prasanth; Rubin A. Parekhji; Suriyaprakash Natarajan; Kanad Basu (CoRR, 2024)

DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs. - Sanjay Das; Anand Menon; Omar Abiola Abioye; Afreen Fatimah Khazi-Syed; Jonathan Edward Lee; Ayush Arunachalam; Shamik Kundu; Pooja Madhusoodhanan; Prasanth Viswanathan Pillai; Rubin A. Parekhji; Arnab Raha; Suvadeep Banerjee; et al. (ACM Great Lakes Symposium on VLSI, 2025)

Innovation Practices Track: Frontiers in Diagnosis and Debug. - Suriyaprakash Natarajan; Saghir A. Shaikh; Wu-Tung Cheng; Sankaran Menon (VTS, 2025)

Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. - Mehmet Onder; Lakshmanan Balasubramanian; Rubin A. Parekhji; Suriyaprakash Natarajan; Sule Ozev (VTS, 2025)