Hardware OS Communication Service and Dynamic Memory Management for RSoCs. - Surya Narayanan; Daniel Chillet; Sébastien Pillement; Ioannis Sourdis (ReConFig, 2011)

Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. - Surya Narayanan; Ludovic Devaux; Daniel Chillet; Sébastien Pillement; Ioannis Sourdis (VLSI-SoC, 2011)

Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era. - Surya Narayanan; Bharath Narasimha Swamy; André Seznec (SBAC-PAD (Workshops), 2014)

An empirical high level performance model for future many-cores. - Surya Narayanan; Bharath Narasimha Swamy; André Seznec (Conf. Computing Frontiers, 2015)

Sequential and Parallel Code Sections are Different: they may require different Processors. - Surya Narayanan; André Seznec (PARMA-DITAM@HiPEAC, 2015)

INXS: Bridging the throughput and energy gap for spiking neural networks. - Surya Narayanan; Ali Shafiee; Rajeev Balasubramonian (IJCNN, 2017)

Moving CNN Accelerator Computations Closer to Data. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian (EMC2@ASPLOS, 2018)

A Case for Dynamic Activation Quantization in CNNs. - Karl Taht; Surya Narayanan; Rajeev Balasubramonian (EMC2@ASPLOS, 2018)

Wire-Aware Architecture and Dataflow for CNN Accelerators. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian; Edouard Giacomin; Hari Kambalasubramanyam; Pierre-Emmanuel Gaillardon (MICRO, 2019)

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. - Surya Narayanan; Karl Taht; Rajeev Balasubramonian; Edouard Giacomin; Pierre-Emmanuel Gaillardon (ISCA, 2020)

CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. - Sumanth Gudaparthi; Sarabjeet Singh; Surya Narayanan; Rajeev Balasubramonian; Visvesh Sathe 001 (HPCA, 2022)