A continuous-time noise-shaping modulator for logarithmic A/D conversion. - Luis Hernández 003; Susana Patón (ISCAS (2), 1999)

A superregenerative receiver for phase and frequency modulated carriers. - Luis Hernández 003; Susana Patón (ISCAS (3), 2002)

A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. - Antonio Di Giandomenico; Susana Patón; Andreas Wiesbauer; Luis Hernández 003; Thomas Pötscher; Lukas Dörrer (ESSCIRC, 2003)

Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. - Luis Hernández 003; Susana Patón (ISCAS (1), 2003)

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. - Susana Patón; Thomas Pötscher; Antonio Di Giandomenico; Klaus Kolhaupt; Luis Hernández 003; Andreas Wiesbauer; Martin Clara; Ramon Frutos (CICC, 2004)

A jitter insensitive continuous-time ΣΔ modulator using transmission lines. - Luis Hernández 003; Pieter Rombouts; Enrique Prefasi; Susana Patón; Mario Garcia; Celia López (ICECS, 2004)

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction. - Luis Hernández 003; Andreas Wiesbauer; Susana Patón; Antonio Di Giandomenico (ISCAS (1), 2004)

A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. - Susana Patón; Antonio Di Giandomenico; Luis Hernández 003; Andreas Wiesbauer; Thomas Pötscher; Martin Clara (IEEE J. Solid State Circuits, 2004)

Synthesis of sigma delta modulators employing continuous time delays. - Luis Hernández 003; Enrique Prefasi; Susana Patón; Pieter Rombouts (ISCAS (4), 2005)

Design of Cascaded Continuous-Time Sigma-Delta Modulators. - Susana Patón; Manuel Sanchez-Renedo; Luis Hernández 003; Enrique Prefasi; Andreas Wiesbauer; Antonio Di Giandomenico; David San Segundo (ICECS, 2006)

A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. - Manuel Sanchez-Renedo; Susana Patón; Luis Hernández 003 (ICECS, 2006)

Spectral shaping of clock jitter errors for continuous time sigma-delta modulators. - Luis Hernández 003; Susana Patón; Andreas Wiesbauer (ISCAS, 2006)

Resolution enhancement of sigma-delta modulators using a tracking digital filter. - Luis Hernández 003; Susana Patón (ICECS, 2008)

An A/D converter based on pulse width modulation and the walsh-hadamard transform. - Luis Hernández 003; Susana Patón; Enrique Prefasi (ICECS, 2008)

Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer. - Enrique Prefasi; Ernesto Pun; Luis Hernández 003; Susana Patón (ICECS, 2009)

A 0.1 mm2, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS. - Enrique Prefasi; Luis Hernández 003; Susana Patón; Andreas Wiesbauer; Richard Gaggl; Ernesto Pun (IEEE J. Solid State Circuits, 2009)

A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. - Luis Hernández 003; Enrique Prefasi; Ernesto Pun; Susana Patón (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. - Enrique Prefasi; Susana Patón; Luis Hernández 003; Richard Gaggl; Andreas Wiesbauer; Jörg Hauptmann (ESSCIRC, 2010)

A time encoded decimation filter for noise shaped power DACs. - Luis Hernández 003; Jorge Fernández 001; Enrique Prefasi; Susana Patón (ISCAS, 2010)

Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters. - Susana Patón; Juan A. Torreño; Enrique Prefasi; Luis Hernández 003 (ISCAS, 2010)

A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm 2 65 nm CMOS Circuit. - Enrique Prefasi; Susana Patón; Luis Hernández 003 (IEEE J. Solid State Circuits, 2011)

Analysis of VCO based noise shaping ADCs linearized by PWM modulation. - Luis Hernández 003; Enrique Prefasi; Susana Patón; Pieter Rombouts (ICECS, 2012)

A distortion corrected passive RC noise shaping ADC for biomedical applications. - Luis Hernández 003; Enrique Prefasi; Susana Patón (ISCAS, 2013)

A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator. - Juan A. Torreño; Susana Patón; Luis Hernández 003; Enrique Prefasi; M. Presicce; G. Paoli (ISCAS, 2013)

A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO. - Enrique Prefasi; Eric Gutierrez; Luis Hernández 003; Susana Patón; Sergio Walter; Ulrich Gaier (ICECS, 2014)

Time difference amplifiers to improve the dynamic range of MASH time encoded ADCs. - Laura Conesa-Peraleja; Susana Patón (MWSCAS, 2014)

A noise coupled ΣΔ architecture using a Non Uniform Quantizer. - Juan A. Torreño; Susana Patón; Laura Conesa-Peraleja; Luis Hernández 003; Dietmar Straeussnigg (NORCAS, 2015)

Signal boosting to extend the bandwidth of oversampled converters. - Laura Conesa-Peraleja; Susana Patón; Dietmar Straeussnigg; Andreas Wiesbauer (ICECS, 2016)

Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array. - Andrés Quintero; Carlos Perez; Eric Gutierrez; Luis Hernández 003; Susana Patón (MWSCAS, 2017)

Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. - Eric Gutierrez; Luis Hernández 003; Susana Patón; Pieter Rombouts (ICECS, 2018)

VCO-ADC Resolution Enhancement Using Maximum Length Sequences. - Luis Hernández 003; Enrique Prefasi; Susana Patón; Eric Gutierrez (ISCAS, 2018)

Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros. - Victor Medina; Leidy Mabel Alvero-Gonzalez; Eric Gutierrez; Susana Patón; Luis Hernández 003 (ICECS, 2019)

Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators. - Pablo Vera; Susana Patón; Dietmar Straeussnigg (ISCAS, 2019)

Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. - Fernando Cardes; Victor Medina; Susana Patón; Luis Hernández 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer. - Pablo Vera; Susana Patón (DCIS, 2020)

A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding. - Victor Medina; Susana Patón; Eric Gutierrez; Luis Hernández 003 (ISCAS, 2020)

Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs. - Eric Gutierrez; Carlos Perez; Susana Patón; Luis Hernández 003 (MWSCAS, 2020)

Optimal reconfiguration instant in ΣΔ Modulators. - Pablo Vera; Dietmar Straeussnigg; Victor Medina; Luis Hernández 003; Susana Patón (ISCAS, 2022)

An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals. - Pablo Vera; Andreas Wiesbauer; Susana Patón (Sensors, 2022)

Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. - Alba Páez-Montoro; Javier De Mena Pacheco; Marisa López-Vallejo; Celia López-Ongil; Susana Patón (DCIS, 2023)

A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. - Victor Medina; Rubén Garvi; Eric Gutierrez; Susana Patón; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Parasitic Capacitance Cancellation and SNR Improvement for Capacitance-to-Digital Converters based on a Switched-Capacitor Feedback. - Michele Noviello; Andrés Quintero; Susana Patón (DCIS, 2024)

A Comparison of Frequency-to-Digital Conversion Architectures in VCO-ADCs Built with Standard Cells. - Alba Páez-Montoro; Celia López-Ongil; Mario García-Valderas; Susana Patón (DCIS, 2024)

A 3rd-order Noise Shaped Multistage Open-Loop Current Controlled Oscillator-based ADC with Non-Linearity Compensation. - Nordin Zbida; Susana Patón; Eric Gutierrez (ISCAS, 2024)

System Analysis of Capacitance-to-Digital Converters Based on a Switched-Capacitor Feedback. - Michele Noviello; Rubén Garvi; Andrés Quintero; Susana Patón (MWSCAS, 2024)

Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal. - Victor Medina; Leidy Mabel Alvero-Gonzalez; Eric Gutierrez; Luis Hernández 003; Susana Patón (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

All-Digital Open-Loop 2nd-order Pulse Shaping Filter VCO-based ADC. - Nordin Zbida; Susana Patón; Eric Gutierrez (ISCAS, 2025)

MWSCAS Guest Editorial Special Issue Based on the 67th International Midwest Symposium on Circuits and Systems. - Marvin Onabajo; Susana Patón; Bibhu Datta Sahoo 003; Hanjun Jiang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)