Impact of stress on various circuit characteristics in 65nm PDSOI technology. - Sushant Suryagandh; Mayank Gupta; Zhiyuan Wu; Srinath Krishnan; Mario Pelella; Jung-Suk Goo; Ciby Thuruthiyil; Judy X. An; Brian Q. Chen; Niraj Subba; Luis Zamudio; James Yonemura; et al. (ESSCIRC, 2007)

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. - Akif Sultan; John Faricelli; Sushant Suryagandh; Hans vanMeer; Kaveri Mathur; James Pattison; Sean Hannon; Greg Constant; Kalyana Kumar; Kevin Carrejo; Joe Meier; Rasit Onur Topaloglu; et al. (ISQED, 2009)