A Hierarchical Approach Test Vector Generation. - Susheel J. Chandra; Janak H. Patel (DAC, 1987)

Test generation in a parallel processing environment. - Susheel J. Chandra; Janak H. Patel (ICCD, 1988)

Accurate logic simulation in the presence of unknowns. - Susheel J. Chandra; Janak H. Patel (ICCAD, 1989)

High performance test generation for accurate defect models in CMOS gate array technology. - Hector R. Sucar; Susheel J. Chandra; David J. Wharton (ICCAD, 1989)

Experimental evaluation of testability measures for test generation (logic circuits). - Susheel J. Chandra; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Techniques to speedup test generation for VLSI circuits - Susheel J. Chandra (1989)

ATPG Based on a Novel Grid-Addressable Latch Element. - Susheel J. Chandra; Tom Ferry; Tushar Gheewala; Kerry Pierce (DAC, 1991)

Use of CrossCheck test technology in practical applications. - Susheel J. Chandra; Tushar Gheewala; Hector R. Sucar; George Swan (VTS, 1991)