Efficient Multiplication and Accumulation of Signed Numbers. - Susheel Ujwal Siddamshetty; Suresh Nambi; Srinivas Boppu; Debapratim Ghosh (iSES, 2022)

Efficient Hardware Architecture for Posit Addition/Subtraction. - Susheel Ujwal Siddamshetty; Srinivas Boppu; Debapratim Ghosh (MCSoC, 2022)

Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. - Ashish Reddy Bommana; Susheel Ujwal Siddamshetty; Pudi Dhilleswararao; Arvind Thumatti K. R.; Srinivas Boppu; M. Sabarimalai Manikandan; Linga Reddy Cenkeramaddi (ACM Trans. Design Autom. Electr. Syst., 2023)