Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. - Sushil Chandra Jain; Anshul Kumar; Shashi Kumar (FPL, 2000)

Evaluation of Various Routing Architectures for Multi-FPGA Boards. - Sushil Chandra Jain; Shashi Kumar; Anshul Kumar (VLSI Design, 2000)

Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards. - Sushil Chandra Jain; Anshul Kumar; Shashi Kumar (FPT, 2002)

Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. - Sushil Chandra Jain; Anshul Kumar; Shashi Kumar (IEEE International Workshop on Rapid System Prototyping, 2002)

Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing. - Sushil Chandra Jain; Anshul Kumar; Shashi Kumar (Des. Autom. Embed. Syst., 2003)