Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. - Susmita Sur-Kolay; Bhargab B. Bhattacharya (FSTTCS, 1988)

The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. - Susmita Sur-Kolay; Bhargab B. Bhattacharya (ICCD, 1991)

Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. - Susmita Sur-Kolay; Bhargab B. Bhattacharya (DAC, 1992)

Efficient Algorithms for Vertex Arboricity of Planar Graphs. - Abhik Roychoudhury; Susmita Sur-Kolay (FSTTCS, 1995)

A unified approach to topology generation and area optimization of general floorplans. - Parthasarathi Dasgupta; Susmita Sur-Kolay; Bhargab B. Bhattacharya (ICCAD, 1995)

VLSI floorplan generation and area optimization using AND-OR graph search. - P. S. Dasgupta; Susmita Sur-Kolay; Bhargab B. Bhattacharya (VLSI Design, 1995)

Slicibility of rectangular graphs and floorplan optimization. - Parthasarathi Dasgupta; Susmita Sur-Kolay (ISPD, 1997)

Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. - Sandip Das 001; Susmita Sur-Kolay; Bhargab B. Bhattacharya (VLSI Design, 1998)

A unified approach to topology generation and optimal sizing of floorplans. - Parthasarathi Dasgupta; Susmita Sur-Kolay; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Fsimac: a fault simulator for asynchronous sequential circuits. - Susmita Sur-Kolay; Marly Roncken; Ken S. Stevens; Parimal Pal Chaudhuri; Rob Roy (Asian Test Symposium, 2000)

Optimal Partitioning for FPGA Based Regular Array Implementations. - Steven Derrien; Sanjay V. Rajopadhye; Susmita Sur-Kolay (PARELEC, 2000)

Topological Routing Amidst Polygonal Obstacles. - Swarup Bhunia; Subhashis Majumder; Ayan Sircar; Susmita Sur-Kolay; Bhargab B. Bhattacharya (VLSI Design, 2000)

Combining Instruction and Loop Level Parallelism for FPGAs. - Steven Derrien; Sanjay V. Rajopadhye; Susmita Sur-Kolay (FCCM, 2001)

Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. - Subhashis Majumder; Susmita Sur-Kolay; Bhargab B. Bhattacharya; Subhas C. Nandy (ISCAS (5), 2001)

Combined instruction and loop parallelism in array synthesis for FPGAs. - Steven Derrien; Sanjay V. Rajopadhye; Susmita Sur-Kolay (ISSS, 2001)

Partitioning Routing Area into Zones with Distinct Pins. - Koushik Sinha; Susmita Sur-Kolay; Bhargab B. Bhattacharya; P. S. Dasgupta (VLSI Design, 2001)

Slicible rectangular graphs and their optimal floorplans. - Parthasarathi Dasgupta; Susmita Sur-Kolay (ACM Trans. Design Autom. Electr. Syst., 2001)

Flavours of Traveling Salesman Problem in VLSI Design. - Susmita Sur-Kolay; Satyajit Banerjee; C. A. Murthy (IICAI, 2003)

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. - Chandra Tirumurti; Sandip Kundu; Susmita Sur-Kolay; Yi-Shing Chang (DATE, 2004)

Virtual Molecular Computing - Emulating DNA Molecules. - Sanjay Goswami; Susmita Sur-Kolay (IWDC, 2004)

Physical Design Trends and Layout-Based Fault Modeling. - Susmita Sur-Kolay; Parthasarathi Dasgupta; Bhargab B. Bhattacharya; Sujit T. Zachariah (VLSI Design, 2004)

Manhattan-diagonal routing in channels and switchboxes. - Sandip Das 001; Susmita Sur-Kolay; Bhargab B. Bhattacharya (ACM Trans. Design Autom. Electr. Syst., 2004)

Fast FPGA Placement using Space-filling Curve. - Pritha Banerjee 001; Subhasis Bhattacharjee; Susmita Sur-Kolay; Sandip Das 001; Subhas C. Nandy (FPL, 2005)

Genetic Algorithm for Double Digest Problem. - Susmita Sur-Kolay; Satyajit Banerjee; Srabani Mukhopadhyaya; C. A. Murthy (PReMI, 2005)

Hot Spots and Zones in a Chip: A Geometrician's View. - Subhashis Majumder; Susmita Sur-Kolay; Subhas C. Nandy; Bhargab B. Bhattacharya; B. Chakraborty (VLSI Design, 2005)

Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. - Sriparna Saha 001; Susmita Sur-Kolay; Sanghamitra Bandyopadhyay; Parthasarathi Dasgupta (ICIT, 2006)

Test Pattern Generation for Power Supply Droop Faults. - Debasis Mitra 002; Subhasis Bhattacharjee; Susmita Sur-Kolay; Bhargab B. Bhattacharya; Sujit T. Zachariah; Sandip Kundu (VLSI Design, 2006)

Fast Robust Intellectual Property Protection for VLSI Physical Design. - Debasri Saha; Susmita Sur-Kolay (ICIT, 2007)

Faster Placer for Island-Style FPGAs. - Pritha Banerjee 001; Susmita Sur-Kolay (ICCTA, 2007)

A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. - Debasri Saha; Parthasarathi Dasgupta; Susmita Sur-Kolay; Samar Sen-Sarma (ICCTA, 2007)

Floorplanning in Modern FPGAs. - Pritha Banerjee 001; Susmita Sur-Kolay; Arijit Bishnu (VLSI Design, 2007)

Nearest Neighbour based Synthesis of Quantum Boolean Circuits. - Amlan Chakrabarti; Susmita Sur-Kolay (Eng. Lett., 2007)

Hierarchical partitioning of VLSI floorplans by staircases. - Subhashis Majumder; Susmita Sur-Kolay; Bhargab B. Bhattacharya; Swarup Kumar Das (ACM Trans. Design Autom. Electr. Syst., 2007)

An Analytical Approach to Direct IP Protection of VLSI Floorplans. - Debasri Saha; Susmita Sur-Kolay (ICIIS, 2008)

Floorplanning. - Susmita Sur-Kolay (Handbook of Algorithms for Physical Design Automation, 2008)

Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design. - Debasri Saha; Susmita Sur-Kolay (ISVLSI, 2009)

Floorplanning for Partial Reconfiguration in FPGAs. - Pritha Banerjee 001; Megha Sangtani; Susmita Sur-Kolay (VLSI Design, 2009)

Encoding of Floorplans through Deterministic Perturbation. - Debasri Saha; Susmita Sur-Kolay (VLSI Design, 2009)

MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. - Sriparna Saha 001; Susmita Sur-Kolay; Parthasarathi Dasgupta; Sanghamitra Bandyopadhyay (Appl. Soft Comput., 2009)

Droop sensitivity of stuck-at fault tests. - Debasis Mitra 002; Susmita Sur-Kolay; Bhargab B. Bhattacharya (IET Comput. Digit. Tech., 2009)

The Double Digest Problem: finding all solutions. - Susmita Sur-Kolay; Satyajit Banerjee; Srabani Mukhopadhyaya; C. A. Murthy (Int. J. Bioinform. Res. Appl., 2009)

Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. - Pritha Banerjee 001; Susmita Sur-Kolay; Arijit Bishnu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

FPGA placement using space-filling curves: Theory meets practice. - Pritha Banerjee 001; Susmita Sur-Kolay; Arijit Bishnu; Sandip Das 001; Subhas C. Nandy; Subhasis Bhattacharjee (ACM Trans. Embed. Comput. Syst., 2009)

A Unified Approach for IP Protection across Design Phases in a Packaged Chip. - Debasri Saha; Susmita Sur-Kolay (VLSI Design, 2010)

Test pattern generation for droop faults. - Debasis Mitra 002; Susmita Sur-Kolay; Bhargab B. Bhattacharya; Sandip Kundu; Ashish Nigam; Sandeep K. Dey (IET Comput. Digit. Tech., 2010)

Robust intellectual property protection of VLSI physical design. - Debasri Saha; Susmita Sur-Kolay (IET Comput. Digit. Tech., 2010)

Synthesis Techniques for Ternary Quantum Logic. - Sudhindu Bikash Mandal; Amlan Chakrabarti; Susmita Sur-Kolay (ISMVL, 2011)

TSV-aware Scan Chain Reordering for 3D IC. - Ayan Datta; Charudhattan Nagarajan; Susmita Sur-Kolay (ISVLSI, 2011)

Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning - Amlan Chakrabarti; Susmita Sur-Kolay; Ayan Chaudhury (CoRR, 2011)

Cone-based placement for field programmable gate arrays. - Pritha Banerjee 001; Debasri Saha; Susmita Sur-Kolay (IET Comput. Digit. Tech., 2011)

Floorplanning for Partially Reconfigurable FPGAs. - Pritha Banerjee 001; Megha Sangtani; Susmita Sur-Kolay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection. - Debasri Saha; Susmita Sur-Kolay (VLSI Design, 2011)

Intellectual property protection and security of SoCs - An embedded tutorial. - Susmita Sur-Kolay (SoCC, 2012)

A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. - Bapi Kar; Susmita Sur-Kolay; Sridhar H. Rangarajan; Chittaranjan A. Mandal (VDAT, 2012)

A Synthesis Method for Quaternary Quantum Logic Circuits. - Sudhindu Bikash Mandal; Amlan Chakrabarti; Susmita Sur-Kolay (VDAT, 2012)

Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. - Susmita Sur-Kolay; Swarup Bhunia (VLSI Design, 2012)

Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol. - Debasri Saha; Susmita Sur-Kolay (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Modular Design for Symmetric Functions Using Quantum Quaternary Logic. - Arighna Deb; Debesh K. Das; Susmita Sur-Kolay (ISED, 2013)

STAIRoute: Global routing using monotone staircase channels. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (ISVLSI, 2013)

A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures. - Arani Bhattacharya; Ansuman Banerjee; Susmita Sur-Kolay; Prasenjit Basu; Bhaskar J. Karmakar (VDAT, 2013)

Trusted sharing of intellectual property in electronic hardware design. - Debasri Saha; Susmita Sur-Kolay (WESS, 2014)

Energy-Aware H.264 Decoding. - Arani Bhattacharya; Ansuman Banerjee; Susmita Sur-Kolay (ICDCIT, 2014)

Synthesis of Ternary Grover's Algorithm. - Sudhindu Bikash Mandal; Amlan Chakrabarti; Susmita Sur-Kolay (ISMVL, 2014)

A novel architecture for QPSK modulation based on time-mode signal processing. - Sumit Saha; Bapi Kar; Susmita Sur-Kolay (VDAT, 2014)

Global Routing Using Monotone Staircases with Minimal Bends. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (VLSID, 2014)

A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. - Arighna Deb; Debesh Kumar Das; Susmita Sur-Kolay (J. Low Power Electron., 2014)

A New Method for Defining Monotone Staircases in VLSI Floorplans. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (ISVLSI, 2015)

Flare reduction in EUV Lithography by perturbation of wire segments. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (VLSI-SoC, 2015)

Approximation algorithms for maximum independent set of a unit disk graph. - Gautam K. Das; Minati De; Sudeshna Kolay; Subhas C. Nandy; Susmita Sur-Kolay (Inf. Process. Lett., 2015)

Quantum Ternary Circuit Synthesis Using Projection Operations. - Sudhindu Bikash Mandal; Amlan Chakrabarti; Susmita Sur-Kolay (J. Multiple Valued Log. Soft Comput., 2015)

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. - Mehran Mozaffari Kermani; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE J. Biomed. Health Informatics, 2015)

Energy-Efficient Long-term Continuous Personal Health Monitoring. - Arsalan Mohsen Nia; Mehran Mozaffari Kermani; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2015)

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. - Chia-Chun Lin; Susmita Sur-Kolay; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification. - Debasri Saha; Susmita Sur-Kolay (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An efficient synthesis method for ternary reversible logic. - Saikat Basu; Sudhindu Bikash Mandal; Amlan Chakrabarti; Susmita Sur-Kolay (ISCAS, 2016)

An early global routing framework for uniform wire distribution in SoCs. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (SoCC, 2016)

A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (VLSID, 2016)

Error tracing in linear and concatenated quantum circuits. - Ritajit Majumdar; Saikat Basu; Priyanka Mukhopadhyay; Susmita Sur-Kolay (CoRR, 2016)

Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip. - Debasri Saha; Susmita Sur-Kolay (IET Comput. Digit. Tech., 2016)

Physiological Information Leakage: A New Frontier in Health Information Security. - Arsalan Mohsen Nia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2016)

Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (ICCD, 2017)

A Method to Reduce Resources for Quantum Error Correction. - Ritajit Majumdar; Saikat Basu; Susmita Sur-Kolay (RC, 2017)

Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs. - Debasri Saha; Susmita Sur-Kolay (VLSID, 2017)

CABA: Continuous Authentication Based on BioAura. - Arsalan Mosenia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Computers, 2017)

Wearable Medical Sensor-Based System Design: A Survey. - Arsalan Mosenia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. - Arsalan Mosenia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (CoRR, 2018)

Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (CoRR, 2018)

Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (CoRR, 2018)

Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test. - Manobendra Nath Mondal; Animesh Basak Chowdhury; Manjari Pradhan; Susmita Sur-Kolay; Bhargab B. Bhattacharya (ATS, 2019)

Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (ISVLSI, 2019)

Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. - Manobennath Mondal; Susmita Sur-Kolay; Bhargab B. Bhattacharya (VLSID, 2019)

Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs. - Debasri Saha; Susmita Sur-Kolay (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Special Session: Quantum Error Correction in Near Term Systems. - Ritajit Majumdar; Susmita Sur-Kolay (ICCD, 2020)

Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost. - Ritajit Majumdar; Susmita Sur-Kolay (ISMVL, 2020)

Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar. - Manobendra Nath Mondal; Susmita Sur-Kolay; Bhargab B. Bhattacharya (ISVLSI, 2020)

Exploiting degeneracy to construct good ternary quantum error correcting code. - Ritajit Majumdar; Susmita Sur-Kolay (CoRR, 2020)

Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate. - Amit Saha; Ritajit Majumdar; Debasri Saha; Amlan Chakrabarti; Susmita Sur-Kolay (CoRR, 2020)

3D reconstruction of spine image from 2D MRI slices along one axis. - Somoballi Ghoshal; Sourav Banu; Amlan Chakrabarti; Susmita Sur-Kolay; Alok Pandit (IET Image Process., 2020)

3D Reconstruction from Micro-CT Slices for Non-Destructive Viewing inside a Fossil. - Somoballi Ghoshal; Partha Bhowmick; Amlan Chakrabarti; Susmita Sur-Kolay; Sanjukta Chakravorti; Dhurjati Sengupta (IVCNZ, 2021)

Optimizing Ansatz Design in QAOA for Max-cut. - Ritajit Majumdar; Dhiraj Madan; Debasmita Bhoumik; Dhinakaran Vinayagamurthy; Shesha Raghunathan; Susmita Sur-Kolay (CoRR, 2021)

Depth Optimized Ansatz Circuit in QAOA for Max-Cut. - Ritajit Majumdar; Debasmita Bhoumik; Dhiraj Madan; Dhinakaran Vinayagamurthy; Shesha Raghunathan; Susmita Sur-Kolay (CoRR, 2021)

FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs. - Mukta Debnath; Animesh Basak Chowdhury; Debasri Saha; Susmita Sur-Kolay (CoRR, 2021)

A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (IET Circuits Devices Syst., 2021)

Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud. - Debasri Saha; Susmita Sur-Kolay (ACM Trans. Embed. Comput. Syst., 2021)

GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs. - Mukta Debnath; Animesh Basak Chowdhury; Debasri Saha; Susmita Sur-Kolay (ITC, 2022)

Memristive Neural Network with Efficient In-Situ Supervised Training. - Santlal Prajaprati; Manobendra Nath Mondal; Susmita Sur-Kolay (SOCC, 2022)

Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. - Kritanta Saha; Pritha Banerjee 001; Susmita Sur-Kolay (VLSI-SoC, 2022)

Stitch-avoiding Global Routing for Multiple E-Beam Lithography. - Kritanta Saha; Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (VLSID, 2022)

Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution. - Mukta Debnath; Animesh Basak Chowdhury; Debasri Saha; Susmita Sur-Kolay (CoRR, 2022)

Efficient Machine-Learning-based decoder for Heavy Hexagonal QECC. - Debasmita Bhoumik; Ritajit Majumdar; Dhiraj Madan; Dhinakaran Vinayagamurthy; Shesha Raghunathan; Susmita Sur-Kolay (CoRR, 2022)

Faster search of clustered marked states with lackadaisical quantum walks. - Amit Saha; Ritajit Majumdar; Debasri Saha; Amlan Chakrabarti; Susmita Sur-Kolay (Quantum Inf. Process., 2022)

Segmentation and Labeling of Vertebra Using SegFormer Architecture. - Archan Ghosh; Debgandhar Ghosh; Somoballi Ghoshal; Amlan Chakrabarti; Susmita Sur-Kolay (CVIP (2), 2023)

Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing. - Somoballi Ghoshal; Shremoyee Goswami; Amlan Chakrabarti; Susmita Sur-Kolay (CoRR, 2023)

AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud. - Mukta Debnath; Krishnendu Guha; Debasri Saha; Susmita Sur-Kolay (CoRR, 2023)

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. - Sudipta Paul 001; Tridib Mukherjee; Pritha Banerjee 001; Susmita Sur-Kolay (Integr., 2023)

Designing Ternary Quantum Error Correcting Codes from Binary Codes. - Ritajit Majumdar; Susmita Sur-Kolay (J. Multiple Valued Log. Soft Comput., 2023)

Test Optimization in Memristor Crossbars Based on Path Selection. - Manobendra Nath Mondal; Susmita Sur-Kolay; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Machine Learning based Decoding of Heavy Hexagonal QECC for Asymmetric Quantum Noise. - Debasmita Bhoumik; Ritajit Majumdar; Dhiraj Madan; Susmita Sur-Kolay (ISVLSI, 2024)

Aggregate Encryption Individual Decryption for FPGA Bitstream Protection on Cloud. - Mukta Debnath; Krishnendu Guha; Debasri Saha; Susmita Sur-Kolay (SEED, 2024)

Optimized QAOA ansatz circuit design for two-body Hamiltonian problems. - Ritajit Majumdar; Dhiraj Madan; Debasmita Bhoumik; Dhinakaran Vinayagamurthy; Shesha Raghunathan; Susmita Sur-Kolay (VLSID, 2024)

Panoptic Segmentation and Labelling of Lumbar Spine Vertebrae using Modified Attention Unet. - Rikathi Pal; Priya Saha; Somoballi Ghoshal; Amlan Chakrabarti; Susmita Sur-Kolay (CoRR, 2024)

Lumbar Spine Tumor Segmentation and Localization in T2 MRI Images Using AI. - Rikathi Pal; Sudeshna Mondal; Aditi Gupta; Priya Saha; Somoballi Ghoshal; Amlan Chakrabarti; Susmita Sur-Kolay (CoRR, 2024)

Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs. - Mukta Debnath; Animesh Basak Chowdhury; Debasri Saha; Susmita Sur-Kolay (CoRR, 2024)

Resource-aware scheduling of multiple quantum circuits on a hardware device. - Debasmita Bhoumik; Ritajit Majumdar; Susmita Sur-Kolay (CoRR, 2024)

FragQC: An efficient quantum error reduction technique using quantum circuit fragmentation. - Saikat Basu; Arnav Das 002; Amit Saha; Amlan Chakrabarti; Susmita Sur-Kolay (J. Syst. Softw., 2024)

Intermediate qutrit-assisted Toffoli gate decomposition with quantum error correction. - Ritajit Majumdar; Amit Saha; Amlan Chakrabarti; Susmita Sur-Kolay (Quantum Inf. Process., 2024)

Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing. - Somoballi Ghoshal; Shreemoyee Goswami; Amlan Chakrabarti; Susmita Sur-Kolay (SN Comput. Sci., 2024)

Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network. - Kritanta Saha; Pritha Banerjee 001; Susmita Sur-Kolay (VLSID, 2025)

Efficient and Fault-Tolerant Memristive Neural Networks with In-Situ Training. - Santlal Prajapat; Manobendra Nath Mondal; Susmita Sur-Kolay (CoRR, 2025)

Efficient Memristive Spiking Neural Networks Architecture with Supervised In-Situ STDP Method. - Santlal Prajapati; Susmita Sur-Kolay; Soumyadeep Dutta (CoRR, 2025)