A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. - Daisaburo Takashima; Susumu Shuto; Iwao Kunishima; Hiroyuki Takenaka; Yukihito Oowaki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 1999)

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. - Ryu Ogiwara; Sumio Tanaka; Yasuo Itoh; Tadashi Miyakawa; Yoshiaki Takeuchi; Sumiko Mano Doumae; Hiroyuki Takenaka; Iwao Kunishima; Susumu Shuto; Osamu Hidaka; Sumito Ohtsuki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 2000)

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. - Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; et al. (ISSCC, 2006)

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (ISSCC, 2009)

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (ISSCC, 2010)

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (IEEE J. Solid State Circuits, 2010)

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. - Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2011)

Sequential Bayesian inference for Weibull distribution parameters with initial hyperparameter optimization for system reliability estimation. - Susumu Shuto; Takashi Amemiya (Reliab. Eng. Syst. Saf., 2022)