Energy-Efficient Hardware Implementation of Spiking-Restricted Boltzmann Machines Using Pseudo-Synaptic Sampling. - Hyunwoo Kim; Suyeon Jang; Uicheol Shin; Masatoshi Ishii; Atsuya Okazaki; Megumi Ito; Akiyo Nomura; Kohji Hosokawa; Sungmin Lee; Matthew J. BrightSky; SangBum Kim (Adv. Intell. Syst., 2025)

QUILL: An Algorithm-Architecture Co-Design for Cache-Local Deformable Attention. - Hyunwoo Oh; Hanning Chen; Sanggeon Yun; Yang Ni 001; Wenjun Huang 001; Tamoghno Das; Suyeon Jang; Mohsen Imani (DATE, 2026)

RIFT: A Single-Bitstream, Runtime-Adaptive FPGA-Based Accelerator for Multimodal AI. - Hyunwoo Oh; Hanning Chen; Sanggeon Yun; Yang Ni 001; Suyeon Jang; Behnam Khaleghi; Fei Wen; Mohsen Imani (DATE, 2026)

T-SAR: A Full-Stack Co-design for CPU-Only Ternary LLM Inference via In-Place SIMD ALU Reorganization. - Hyunwoo Oh; KyungIn Nam; Rajat Bhattacharjya; Hanning Chen; Tamoghno Das; Sanggeon Yun; Suyeon Jang; Andrew Ding; Nikil D. Dutt; Mohsen Imani (DATE, 2026)

TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design. - Hyunwoo Oh; Sungheon Jeong 001; Suyeon Jang; Hanning Chen; Sanggeon Yun; Tamoghno Das; Mohsen Imani (CoRR, 2026)

TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI. - Hyunwoo Oh; Hanning Chen; Sanggeon Yun; Yang Ni 001; Suyeon Jang; Behnam Khaleghi; Fei Wen; Mohsen Imani (CoRR, 2026)