Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments. - Sven Gesper; Moritz Weißbrich; Stephan Nolting; Tobias Stuckenberg; Pekka Jääskeläinen; Holger Blume; Guillermo Payá-Vayá (SAMOS, 2019)

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. - Sven Gesper; Moritz Weißbrich; Tobias Stuckenberg; Pekka Jääskeläinen; Holger Blume; Guillermo Payá-Vayá (Int. J. Parallel Program., 2021)

TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. - Johannes Knödtel; Hector Gerardo Muñoz Hernandez; Alexander Lehnert; Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Marc Reichenbach (ARC, 2023)

Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency. - Michael Beyer; Sven Gesper; Andre Guntoro; Guillermo Payá-Vayá; Holger Blume (ASAP, 2023)

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Christoph Riggers; Oliver Renke; Till Fiedler; Jakob Marten; Tobias Stuckenberg; Holger Blume; Christian Weis; Lukas Steiner; Chirag Sudarshan; et al. (DATE, 2023)

N2V2PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture. - Sven Gesper; Gia Bao Thieu; Daniel Köhler; Markus Kock; Tim Berthold; Oliver Renke; Holger Blume; Guillermo Payá-Vayá (ICCE-Berlin, 2023)

PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations. - Sven Gesper; Fabian Stuckmann; Lucy Wöbbekind; Guillermo Payá-Vayá (SAMOS, 2023)

Multi-Level Prototyping of a Vertical Vector AI Processing System. - Frederik Kautz; Sven Gesper; Gia Bao Thieu; Hans-Martin Blüthgen; Holger Blume; Guillermo Payá-Vayá (ASAP, 2024)

A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor. - Sven Gesper; Daniel Köhler; Gia Bao Thieu; Jasper Homann; Frank Meinl; Holger Blume; Guillermo Payá-Vayá (SAMOS, 2024)

DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá (ACM Trans. Archit. Code Optim., 2025)