Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. - Sven-Ole Voigt; Thomas Teufel (FPL, 2007)

Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms. - Sven-Ole Voigt; Thomas Teufel (FCCM, 2008)

Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platforms. - Sven-Ole Voigt (2008)

An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier. - Malte Baesler; Sven-Ole Voigt; Thomas Teufel (FPL, 2010)

A radix-10 digit recurrence division unit with a constant digit selection function. - Malte Baesler; Sven-Ole Voigt; Thomas Teufel (ICCD, 2010)

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA. - Malte Baesler; Sven-Ole Voigt; Thomas Teufel (Int. J. Reconfigurable Comput., 2010)

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing. - Sven-Ole Voigt; Malte Baesler; Thomas Teufel (J. Syst. Archit., 2010)

FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers. - Malte Baesler; Sven-Ole Voigt; Thomas Teufel (ReConFig, 2011)

A multi-core FPGA-based SoC architecture with domain segregation. - Daniel Kliem; Sven-Ole Voigt (ReConFig, 2012)

An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs. - Daniel Kliem; Sven-Ole Voigt (FPL, 2013)

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs. - Malte Baesler; Sven-Ole Voigt (Int. J. Reconfigurable Comput., 2013)

Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning. - Daniel Kliem; Sven-Ole Voigt (Microprocess. Microsystems, 2014)