A New Retiming Algorithm for Circuit Design. - Sven Simon 001; Ernst G. Bernard; Matthias Sauer 001; Josef A. Nossek (ISCAS, 1994)

Retiming of Circuits Containing Multiplexers. - Sven Simon 001; Johann Hofner; Josef A. Nossek (ISCAS, 1995)

Retiming of synchronous circuits with variable topology. - Sven Simon 001; Ralf Bucher; Josef A. Nossek (VLSI Design, 1995)

Built-in self test architectures for multistage interconnection networks. - Ernst G. Bernard; Sven Simon 001; Josef A. Nossek (ED&TC, 1996)

Low Power CORDIC Implementation Using Redundant Number Representation. - Christian V. Schimpfle; Sven Simon 001; Josef A. Nossek (ASAP, 1997)

Entwurf von Datenpfaden in schnellen integrierten Schaltungen. - Sven Simon 001 (Shaker, 1997)

High-level circuit modeling for power estimation. - Christian V. Schimpfle; Sven Simon 001; Josef A. Nossek (ICECS, 1999)

Device level based cell modeling for fast power estimation. - Christian V. Schimpfle; Sven Simon 001; Josef A. Nossek (ISCAS (1), 1999)

Low power datapath design using transformation similar to temporal localization of SFGs. - Sven Simon 001; Marek Wróblewski (ISCAS (1), 1999)

Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms. - Peter Rieder; Sven Simon 001; Christian V. Schimpfle (J. VLSI Signal Process., 1999)

Low power transformation of datapath architectures with cyclic SFGs. - Marek Wróblewski; Sven Simon 001; Josef A. Nossek (ISCAS, 2000)

Low power register file architecture for application specific DSPs. - Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; S. Wolter; Steffen Buch; Marek Wróblewski; Josef A. Nossek (ISCAS (4), 2002)

A power efficient register file architecture using master latch sharing. - Marek Wróblewski; Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; Wilhelm Pieper; Josef A. Nossek (ISCAS (5), 2003)

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core. - Andreas Wortmann 002; Sven Simon 001; Matthias Müller 002 (DATE, 2004)

The impact of clock gating schemes on the power dissipation of synthesizable register files. - Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; Michael Kugel; Tim Schoenauer (ISCAS (2), 2004)

An instruction set for the efficient implementation of the CORDIC algorithm. - Sven Simon 001; Matthias Müller 002; Holger Gryska; Andreas Wortmann 002; Steffen Buch (ISCAS (2), 2004)

Register Isolation for Synthesizable Register Files. - Matthias Müller 002; Andreas Wortmann 002; Dominik Mader; Sven Simon 001 (PATMOS, 2004)

A power dissipation comparison of ALU-architectures for ASIPs. - Vijayakumar Kalyanaraman; Matthias Müller 002; Sven Simon 001; Mario Steinert; Holger Gryska (ECCTD, 2005)

Power reduction of ASIPs by distributing the workload on several ASIP-instances. - Vijayakumar Kalyanaraman; Matthias Müller 002; Sven Simon 001; Mario Steinert; Holger Gryska (ECCTD, 2005)

Datenskalierung für die verlustleistungsarme Signalverarbeitung in Prozessorsystemen. - Matthias Müller 002; Sven Simon 001 (GI Jahrestagung (1), 2005)

Low power synthesizable register files for processor and IP cores. - Matthias Müller 002; Sven Simon 001; Holger Gryska; Andreas Wortmann 002; Steffen Buch (Integr., 2006)

Acceleration of a finite-difference method with general purpose GPUs - Lesson learned. - Ana Balevic; Lars Rockstroh; Wenbin Li 001; Jürgen Hillebrand; Sven Simon 001; Andreas Tausendfreund; Stefan Patzelt; Gert Goch (CIT, 2008)

Accelerating Simulations of Light Scattering Based on Finite-Difference Time-Domain Method with General Purpose GPUs. - Ana Balevic; Lars Rockstroh; Andreas Tausendfreund; Stefan Patzelt; Gert Goch; Sven Simon 001 (CSE, 2008)

Using Arithmetic Coding for Reduction of Resulting Simulation Data Size on Massively Parallel GPGPUs. - Ana Balevic; Lars Rockstroh; Marek Wróblewski; Sven Simon 001 (PVM/MPI, 2008)

Memory-efficient parallelization of JPEG-LS with relaxed context update. - Simeon Wahl; Zhe Wang 008; Chensheng Qiu; Marek Wróblewski; Lars Rockstroh; Sven Simon 001 (PCS, 2010)

An image filter technique to relax particle image velocimetry. - Lars Rockstroh; Simeon Wahl; Zhe Wang 008; Philipp Werner; Sven Simon 001 (EUSIPCO, 2011)

Exploitation of context classification for parallel pixel coding in JPEG-LS. - Simeon Wahl; Haitham A. Tantawy; Zhe Wang 008; Philipp Werner; Sven Simon 001 (ICIP, 2011)

On the numerical sensitivity of computer simulations on hybrid and parallel computing systems. - Wenbin Li 001; Sven Simon 001; Steffen Kieß (HPCS, 2011)

A memory efficient parallel lossless image compression engine for high performance embedded systems. - Zhe Wang 008; Anto Y. Michael; Simeon Wahl; Philipp Werner; Sven Simon 001 (ISPA, 2011)

In Situ Power Analysis of General Purpose Graphical Processing Units. - M. Z. Shaikh; Mireille Grégoire; W. Li; Marek Wróblewski; Sven Simon 001 (PDP, 2011)

Fast and Context-Free Lossless Image Compression Algorithm Based on JPEG-LS. - Yurij Gera; Zhe Wang 008; Sven Simon 001; Thomas Richter 005 (DCC, 2012)

Fast lossless image compression with 2D Golomb parameter adaptation based on JPEG-LS. - Zhe Wang 008; Michael J. Klaiber; Yurij Gera; Sven Simon 001; Thomas Richter 005 (EUSIPCO, 2012)

A memory-efficient parallel single pass architecture for connected component labeling of streamed images. - Michael J. Klaiber; Lars Rockstroh; Zhe Wang 008; Yousef Baroud; Sven Simon 001 (FPT, 2012)

Relaxation of particle image velocimetry based on single autocorrelation of filtered motion blurring. - T. Lefeure; Lars Rockstroh; Michael J. Klaiber; N. Fortier; Sven Simon 001 (ICASSP, 2012)

Correlation and convolution of image data using fermat number transform based on two's complement. - Lars Rockstroh; Michael J. Klaiber; Sven Simon 001 (ICASSP, 2012)

On the JPEG 2000 ultrafast mode. - Thomas Richter 005; Sven Simon 001 (ICIP, 2012)

SSPQ - spatial domain perceptual image codec based on subsampling and perceptual quantization. - Zhe Wang 008; Sven Simon 001; Michael J. Klaiber; Silvia Ahmed; Thomas Richter 005 (ICIP, 2012)

Memory efficient lossless compression of image sequences with JPEG-LS and temporal prediction. - Zhe Wang 008; Debasish Chanda; Sven Simon 001; Thomas Richter 005 (PCS, 2012)

Stream Processing of Scientific Big Data on Heterogeneous Platforms - Image Analytics on Big Data in Motion. - Seyyed Mahdi Najmabadi; Michael J. Klaiber; Zhe Wang 008; Yousef Baroud; Sven Simon 001 (CSE, 2013)

High Throughput Coding of Video Signals. - Thomas Richter 005; Sven Simon 001 (DCC, 2013)

A high-throughput FPGA architecture for parallel connected components analysis based on label reuse. - Michael J. Klaiber; Donald G. Bailey; Silvia Ahmed; Yousef Baroud; Sven Simon 001 (FPT, 2013)

Coding strategies and performance analysis of GPU accelerated image compression. - Thomas Richter 005; Sven Simon 001 (PCS, 2013)

Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures. - Ghada Dessouky; Michael J. Klaiber; Donald G. Bailey; Sven Simon 001 (FPL, 2014)

High throughput hardware architectures for asymmetric numeral systems entropy coding. - Seyyed Mahdi Najmabadi; Zhe Wang 008; Yousef Baroud; Sven Simon 001 (ISPA, 2015)

Visually lossless image compression extension for JPEG based on just-noticeable distortion evaluation. - Zhe Wang 008; Sven Simon 001; Yousef Baroud; Seyyed Mahdi Najmabadi (IWSSIP, 2015)

Low Complexity Pixel Domain Perceptual Image Compression via Adaptive Down-Sampling. - Zhe Wang 008; Sven Simon 001 (DCC, 2016)

Online Bandwidth Reduction Using Dynamic Partial Reconfiguration. - Seyyed Mahdi Najmabadi; Zhe Wang 008; Yousef Baroud; Sven Simon 001 (FCCM, 2016)

Low complexity perceptual image coding by just-noticeable difference model based adaptive downsampling. - Zhe Wang 008; Yousef Baroud; Seyyed Mahdi Najmabadi; Sven Simon 001 (PCS, 2016)

Architecture for parallelizing decoding of marker-free variable length code streams. - Yousef Baroud; José Manuel Mariños Velarde; Sven Simon 001 (SPA, 2016)

A Resource-Efficient Hardware Architecture for Connected Component Analysis. - Michael J. Klaiber; Donald G. Bailey; Yousef O. Baroud; Sven Simon 001 (IEEE Trans. Circuits Syst. Video Technol., 2016)

Hardware-based architecture for asymmetric numeral systems entropy decoder. - Seyyed Mahdi Najmabadi; Harsimran Singh Tungal; Trung-Hieu Tran; Sven Simon 001 (DASIP, 2017)

Light-field image compression based on variational disparity estimation and motion-compensated wavelet decomposition. - Trung-Hieu Tran; Yousef Baroud; Zhe Wang 008; Sven Simon 001; David Taubman (ICIP, 2017)

Variational disparity estimation framework for plenoptic images. - Trung-Hieu Tran; Zhe Wang 008; Sven Simon 001 (ICME, 2017)

A resource-efficient monitoring architecture for hardware accelerated self-adaptive online data stream compression. - Seyyed Mahdi Najmabadi; Prajwala Pandit; Trung-Hieu Tran; Sven Simon 001 (SPA, 2017)

Analyzing the Effect and Performance of Lossy Compression on Aeroacoustic Simulation of Gas Injector. - Seyyed Mahdi Najmabadi; Philipp Offenhäuser; Moritz Hamann; Guhathakurta Jajnabalkya; Fabian Hempert; Colin W. Glass; Sven Simon 001 (Comput., 2017)

GPU-Accelerated Light-Field Image Super-Resolution. - Trung-Hieu Tran; Gasim Mammadov; Kaicong Sun; Sven Simon 001 (ACOMP, 2018)

Variational Disparity Estimation Framework for Plenoptic Image. - Trung-Hieu Tran; Zhe Wang 008; Sven Simon 001 (CoRR, 2018)

Sub-Pixel Registration Technique for X-ray Phase Contrast Imaging. - Hamish Bradley; Donald G. Bailey; Steven Le Moan; Peter Gaenz; Sven Simon 001 (IVCNZ, 2019)

A JND-Based Pixel-Domain Algorithm and Hardware Architecture for Perceptual Image Coding. - Zhe Wang 008; Trung-Hieu Tran; Ponnanna Kelettira Muthappa; Sven Simon 001 (J. Imaging, 2019)

Comparative Study and Proof of Single-Pass Connected Components Algorithms. - Michael J. Klaiber; Donald G. Bailey; Sven Simon 001 (J. Math. Imaging Vis., 2019)

Architecture for parallel marker-free variable length streams decoding. - Yousef Baroud; José Manuel Mariños Velarde; Zhe Wang 008; Steffen Kieß; Seyyed Mahdi Najmabadi; Guhathakurta Jajnabalkya; Sven Simon 001 (J. Real Time Image Process., 2019)

A single-cycle parallel multi-slice connected components analysis hardware architecture. - Michael J. Klaiber; Donald G. Bailey; Sven Simon 001 (J. Real Time Image Process., 2019)

An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder. - Seyyed Mahdi Najmabadi; Trung-Hieu Tran; Sherif Eissa; Harsimran Singh Tungal; Sven Simon 001 (J. Signal Process. Syst., 2019)

FDRN: A Fast Deformable Registration Network for Medical Images. - Kaicong Sun; Sven Simon 001 (CoRR, 2020)

Multi-frame super-resolution reconstruction based on mixed Poisson-Gaussian noise. - Kaicong Sun; Trung-Hieu Tran; Roman Krawtschenko; Sven Simon 001 (Signal Process. Image Commun., 2020)

Making Historical Gyroscopes Alive - 2D and 3D Preservations by Sensor Fusion and Open Data Access. - Dieter Fritsch; Jörg F. Wagner; Beate Ceranski; Sven Simon 001; Maria Niklaus; Kun Zhan; Gasim Mammadov (Sensors, 2021)

GVLD: A Fast and Accurate GPU-Based Variational Light-Field Disparity Estimation Approach. - Trung-Hieu Tran; Gasim Mammadov; Sven Simon 001 (IEEE Trans. Circuits Syst. Video Technol., 2021)

Bilateral Spectrum Weighted Total Variation for Noisy-Image Super-Resolution and Image Denoising. - Kaicong Sun; Sven Simon 001 (IEEE Trans. Signal Process., 2021)

Computational scatter correction in near real-time with a fast Monte Carlo photon transport model for high-resolution flat-panel CT. - Ammar Alsaffar; Steffen Kieß; Kaicong Sun; Sven Simon 001 (J. Real Time Image Process., 2022)

FL-MISR: fast large-scale multi-image super-resolution for computed tomography based on multi-GPU acceleration. - Kaicong Sun; Trung-Hieu Tran; Guhathakurta Jajnabalkya; Sven Simon 001 (J. Real Time Image Process., 2022)

A GPU-accelerated light-field super-resolution framework based on mixed noise model and weighted regularization. - Trung-Hieu Tran; Kaicong Sun; Sven Simon 001 (J. Real Time Image Process., 2022)

3DVSR: 3D EPI volume-based approach for angular and spatial light field image super-resolution. - Trung-Hieu Tran; Jan Berberich; Sven Simon 001 (Signal Process., 2022)

An FPGA-Based Residual Recurrent Neural Network for Real-Time Video Super-Resolution. - Kaicong Sun; Maurice Koch; Zhe Wang 008; Slavisa Jovanovic; Hassan Rabah; Sven Simon 001 (IEEE Trans. Circuits Syst. Video Technol., 2022)

A resolution enhancement plug-in for deformable registration of medical images. - Kaicong Sun; Sven Simon 001 (Biomed. Signal Process. Control., 2023)

Multi-material blind beam hardening correction in near real-time based on non-linearity adjustment of projections. - Ammar Alsaffar; Kaicong Sun; Sven Simon 001 (J. Real Time Image Process., 2023)