Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling. - Vijay Janapa Reddi; Svilen Kanev; Wonyoung Kim; Simone Campanoni; Michael D. Smith 001; Gu-Yeon Wei; David M. Brooks (MICRO, 2010)

Portable trace compression through instruction interpretation. - Svilen Kanev; Robert Cohn (ISPASS, 2011)

Voltage Noise in Production Processors. - Vijay Janapa Reddi; Svilen Kanev; Wonyoung Kim; Simone Campanoni; Michael D. Smith 001; Gu-Yeon Wei; David M. Brooks (IEEE Micro, 2011)

XIOSim: power-performance modeling of mobile x86 cores. - Svilen Kanev; Gu-Yeon Wei; David M. Brooks (ISLPED, 2012)

Characterizing and evaluating voltage noise in multi-core near-threshold processors. - Xuan Zhang 001; Tao Tong; Svilen Kanev; Sae Kyu Lee; Gu-Yeon Wei; David M. Brooks (ISLPED, 2013)

Tradeoffs between power management and tail latency in warehouse-scale applications. - Svilen Kanev; Kim M. Hazelwood; Gu-Yeon Wei; David M. Brooks (IISWC, 2014)

HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs. - Simone Campanoni; Kevin Brownell; Svilen Kanev; Timothy M. Jones 001; Gu-Yeon Wei; David M. Brooks (ISCA, 2014)

Profiling a Warehouse-Scale Computer. - Svilen Kanev; Juan Pablo Darago; Kim M. Hazelwood; Parthasarathy Ranganathan; Tipp Moseley; Gu-Yeon Wei; David M. Brooks (IEEE Micro, 2016)

Mallacc: Accelerating Memory Allocation. - Svilen Kanev; Sam Likun Xi; Gu-Yeon Wei; David M. Brooks (ASPLOS, 2017)

Automatically accelerating non-numerical programs by architecture-compiler co-design. - Simone Campanoni; Kevin Brownell; Svilen Kanev; Timothy M. Jones 001; Gu-Yeon Wei; David M. Brooks (Commun. ACM, 2017)

CARB: A C-State Power Management Arbiter for Latency-Critical Workloads. - Xin Zhan; Reza Azimi; Svilen Kanev; David M. Brooks; Sherief Reda (IEEE Comput. Archit. Lett., 2017)

AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers. - Nayana Prasad Nagendra; Grant Ayers; David I. August; Hyoun Kyu Cho; Svilen Kanev; Christos Kozyrakis; Trivikram Krishnamurthy; Heiner Litz; Tipp Moseley; Parthasarathy Ranganathan (IEEE Micro, 2020)

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. - Sagar Karandikar; Aniruddha N. Udipi; Junsun Choi; Joonho Whangbo; Jerry Zhao; Svilen Kanev; Edwin Lim; Jyrki Alakuijala; Vrishab Madduri; Yakun Sophia Shao; Borivoje Nikolic; Krste Asanovic; et al. (ISCA, 2023)

EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching. - Nayana Prasad Nagendra; Bhargav Reddy Godala; Ishita Chaturvedi; Atmn Patel; Svilen Kanev; Tipp Moseley; Jared Stark; Gilles A. Pokam; Simone Campanoni; David I. August (ISCA, 2023)

Characterizing a Memory Allocator at Warehouse Scale. - Zhuangzhuang Zhou; Vaibhav Gogte; Nilay Vaish; Chris Kennelly; Patrick Xia 001; Svilen Kanev; Tipp Moseley; Christina Delimitrou; Parthasarathy Ranganathan (ASPLOS (3), 2024)

Correct Wrong Path. - Bhargav Reddy Godala; Sankara Prasad Ramesh; Krishnam Tibrewala; Chrysanthos Pepi; Gino Chacon; Svilen Kanev; Gilles A. Pokam; Daniel A. Jiménez; Paul V. Gratz; David I. August (CoRR, 2024)

Correct Wrong Path. - Bhargav Reddy Godala; Sankara Prasad Ramesh; Krishnam Tibrewala; Chrysanthos Pepi; Gino Chacon; Svilen Kanev; Gilles A. Pokam; Alberto Ros 001; Daniel A. Jiménez; Paul V. Gratz; David I. August (IEEE Comput. Archit. Lett., 2025)