Joint power and channel allocation for outage probability minimization in cognitive radio ad hoc networks. - Tamaghna Acharya; Swagata Mandal; Santi P. Maity (COMSNETS, 2013)

FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code. - Swagata Mandal; Suman Sau; Amlan Chakrabarti; Sushanta Kumar Pal; Subhasish Chattopadhyay (ATS, 2015)

FPGA Based Novel High Speed DAQ System Design with Error Correction. - Swagata Mandal; Suman Sau; Amlan Chakrabarti; Jogendra Saini; Sushanta Kumar Pal; Subhasish Chattopadhyay (ISVLSI, 2015)

A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code. - Swagata Mandal; Rourab Paul; Suman Sau; Amlan Chakrabarti; Subhasis Chattopadhyay (CoRR, 2015)

FPGA based High Speed Data Acquisition System for High Energy Physics Application. - Swagata Mandal; Suman Sau; Amlan Chakrabarti; Subhasis Chattopadhyay (CoRR, 2015)

High speed fault tolerant secure communication for muon chamber using fpga based gbt emulator. - Suman Sau; Swagata Mandal; Jogender Saini; Amlan Chakrabarti; Subhasis Chattopadhyay (CoRR, 2015)

Outage Minimized Joint Power and Channel Allocation in Multihop Cognitive Radio Networks: A Lifetime-Centric Approach. - Tamaghna Acharya; Santi P. Maity; Swagata Mandal (Wirel. Pers. Commun., 2015)

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code. - Swagata Mandal; Rourab Paul; Suman Sau; Amlan Chakrabarti; Subhasis Chattopadhyay (IEEE Embed. Syst. Lett., 2016)

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. - Swagata Mandal; Rourab Paul; Suman Sau; Amlan Chakrabarti; Subhasis Chattopadhyay (Microprocess. Microsystems, 2017)

Lightweight ASIC Implementation of AEGIS-128. - Anubhab Baksi; Vikramkumar Pudi; Swagata Mandal; Anupam Chattopadhyay (ISVLSI, 2018)

ReRAM-based In-Memory Computation of Galois Field arithmetic. - Swagata Mandal; Debjyoti Bhattacharjee; Yaswanth Tavva; Anupam Chattopadhyay (VLSI-SoC, 2018)

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code. - Swagata Mandal; Yaswanth Tavva; Debjyoti Bhattacharjee; Anupam Chattopadhyay (VLSI-SoC (Selected Papers), 2018)

iMACE: In-Memory Acceleration of Classic McEliece Encoder. - Karthikeyan Nagarajan; Sina Sayyah Ensan; Swagata Mandal; Swaroop Ghosh; Anupam Chattopadhyay (ISVLSI, 2019)

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA. - Swagata Mandal; Sreetama Sarkar; Ming Ming Wong; Anupam Chattopadhyay; Amlan Chakrabarti (VLSID, 2019)

Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform. - Swagata Mandal; Amlan Chakrabarti; Srinivasu Bodapati (IEEE Trans. Aerosp. Electron. Syst., 2021)

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture. - Paresh Baidya; Swagata Mandal; Rourab Paul (CoRR, 2022)

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable Architecture. - Paresh Baidya; Swagata Mandal; Rourab Paul (IEEE Access, 2024)

Efficient Implementation of Knuth Yao Sampler on Reconfigurable Hardware. - Paresh Baidya; Rourab Paul; Swagata Mandal; Sumit Kumar Debnath (IEEE Comput. Archit. Lett., 2024)

A Novel Architecture using Dynamic Computing Nodes to Improve Multi-Access Edge Cluster Productivity. - Biswadeep Chatterjee; Swagata Mandal; Amlan Chakrabarti; Sayan Chatterjee (ISVLSI, 2025)

High-speed system-on-chip-based platform for real-time crop disease and pest detection using deep learning techniques. - MD Tausif Mallick; D. Omkar Murty; Ranita Pal; Swagata Mandal; Himadri Nath Saha; Amlan Chakrabarti (Comput. Electr. Eng., 2025)