Dual-pipeline heterogeneous ASIP design. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran (CODES+ISSS, 2004)

Application specific forwarding network and instruction encoding for multi-pipe ASIPs. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran; Aleksandar Ignjatovic (CODES+ISSS, 2006)

Customization of application specific heterogeneous multi-pipeline processors. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran (DATE, 2006)

Heterogeneous multi-pipeline application specific instruction-set processor design and implementation. - Swarnalatha Radhakrishnan (2006)

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran; Aleksandar Ignjatovic (IET Comput. Digit. Tech., 2009)

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. - Mohammad Shihabul Haque; Roshan G. Ragel; Jude Angelo Ambrose; Swarnalatha Radhakrishnan; Sri Parameswaran (CODES+ISSS, 2012)

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Swarnalatha Radhakrishnan; Roshan G. Ragel; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (DATE, 2013)

DRMA: dynamically reconfigurable MPSoC architecture. - Lawrance Zhang; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Roshan G. Ragel; Swarnalatha Radhakrishnan; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2013)

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. - Roshan G. Ragel; Swarnalatha Radhakrishnan; Jude Angelo Ambrose; Sri Parameswaran (VLSI Design, 2013)

Axis2UNO: Web Services Enabled Openoffice.org. - B. A. N. M. Bambarasinghe; H. M. S. Huruggamuwa; Roshan G. Ragel; Swarnalatha Radhakrishnan (CoRR, 2014)

Loop Unrolling in Multi-pipeline ASIP Design. - Rajitha Navarathna; Swarnalatha Radhakrishnan; Roshan G. Ragel (CoRR, 2014)

Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study. - Roshan G. Ragel; Swarnalatha Radhakrishnan; Jude Angelo Ambrose (CoRR, 2014)

Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. - Isuru Nawinne; Haris Javaid; Roshan G. Ragel; Swarnalatha Radhakrishnan; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)