Exploiting Fine-Grain Parallelism of IDEA Using Xilinx FPGA. - Zexin Pan; Srikanth Venkateswaran; Swathi Tanjore Gurumani; B. Earl Wells (PDCS, 2003)

Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++. - Swathi Tanjore Gurumani; Aleksandar Milenkovic (ACM Southeast Regional Conference, 2004)

Performance Analysis of Coarse-Grained Parallel Particle Swarm Optimization. - Swathi Tanjore Gurumani; Mathew M. Noel; B. Earl Wells; Thomas C. Jannett (PDCS, 2006)

Dynamic Power Management in Power-Aware Reconfigurable System-on-Chip Architectures. - Swathi Tanjore Gurumani; B. Earl Wells (ESA, 2007)

Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures. - Swathi Tanjore Gurumani; B. Earl Wells (ERSA, 2007)

Hardware Coprocessor Synthesis from an ANSI C Specification. - Sumit Ahuja; Swathi T. Gurumani; Chad Spackman; Sandeep K. Shukla (IEEE Des. Test Comput., 2009)

High-level synthesis of multiple dependent CUDA kernels on FPGA. - Swathi T. Gurumani; Hisham Cholakkal; Yun Liang 001; Kyle Rupnow; Deming Chen (ASP-DAC, 2013)

High-level synthesis with behavioral level multi-cycle path analysis. - Hongbin Zheng; Swathi T. Gurumani; Liwei Yang; Deming Chen; Kyle Rupnow (FPL, 2013)

Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. - Swathi T. Gurumani; Jacob Tolar; Yao Chen 008; Yun Liang 001; Kyle Rupnow; Deming Chen (FCCM, 2014)

Fast and effective placement and routing directed high-level synthesis for FPGAs. - Hongbin Zheng; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (FPGA, 2014)

New solutions for system-level and high-level synthesis (Invited paper). - Wei Zuo; Hongbin Zheng; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (ISIC, 2014)

High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. - Hongbin Zheng; Swathi T. Gurumani; Liwei Yang; Deming Chen; Kyle Rupnow (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

System-level design solutions: Enabling the IoT explosion. - Liwei Yang; Yao Chen 008; Wei Zuo; Tan Nguyen; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (ASICON, 2015)

Behavioral-level IP integration in high-level synthesis. - Liwei Yang; Swathi T. Gurumani; Deming Chen; Kyle Rupnow (FPT, 2015)

JIT trace-based verification for high-level synthesis. - Liwei Yang; Magzhan Ikram; Swathi T. Gurumani; Suhaib A. Fahmy; Deming Chen; Kyle Rupnow (FPT, 2015)

Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. - Zelei Sun; Keith A. Campbell; Wei Zuo; Kyle Rupnow; Swathi T. Gurumani; Frederic Doucet; Deming Chen (ASP-DAC, 2016)

Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. - Keith A. Campbell; Leon He; Liwei Yang; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (DAC, 2016)

Real-time system-level implementation of a telepresence robot using an embedded GPU platform. - Muhammad Teguh Satria; Swathi T. Gurumani; Wang Zheng; Keng Peng Tee; Augustine Koh; Pan Yu; Kyle Rupnow; Deming Chen (DATE, 2016)

AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. - Liwei Yang; Swathi T. Gurumani; Deming Chen; Kyle Rupnow (FCCM, 2016)

High Level Synthesis of Complex Applications: An H.264 Video Decoder. - Xinheng Liu; Yao Chen 008; Tan Nguyen; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (FPGA, 2016)

FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler. - Tan Nguyen; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (FPGA, 2016)

Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). - Liwei Yang; Swathi T. Gurumani; Suhaib A. Fahmy; Deming Chen; Kyle Rupnow (FPGA, 2016)

SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. - Tan Nguyen; Yao Chen 008; Kyle Rupnow; Swathi T. Gurumani; Deming Chen (ISVLSI, 2016)

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. - Deming Chen; Jason Cong; Swathi T. Gurumani; Wen-mei W. Hwu; Kyle Rupnow; Zhiru Zhang (IET Cyper-Phys. Syst.: Theory & Appl., 2016)

FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. - Ying Chen; Tan Nguyen; Yao Chen 008; Swathi T. Gurumani; Yun Liang 001; Kyle Rupnow; Jason Cong; Wen-mei W. Hwu; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. - Yao Chen 008; Swathi T. Gurumani; Yun Liang 001; Guofeng Li; Donghui Guo; Kyle Rupnow; Deming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. - Keith A. Campbell; David Lin; Leon He; Liwei Yang; Swathi T. Gurumani; Kyle Rupnow; Subhasish Mitra; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)