A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (CICC, 2006)

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. - Rong-Jyi Yang; Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

A Multi-Band Burst-Mode Clock and Data Recovery Circuit. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (IEICE Trans. Electron., 2007)

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

A receiver architecture for intra-band carrier aggregation. - Sy-Chyuan Hwu; Behzad Razavi (VLSIC, 2014)

An RF Receiver for Intra-Band Carrier Aggregation. - Sy-Chyuan Hwu; Behzad Razavi (IEEE J. Solid State Circuits, 2015)