Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits. - Hans-Joachim Wunderlich; Sybille Hellebrand (FTCS, 1988)

Automatisierung des Entwurfs vollständig testbarer Schaltungen. - Sybille Hellebrand; Hans-Joachim Wunderlich (GI Jahrestagung (2), 1988)

The Pseudo-Exhaustive Test of Sequential Circuits. - Sybille Hellebrand; Hans-Joachim Wunderlich (ITC, 1989)

Tools and devices supporting the pseudo-exhaustive test. - Sybille Hellebrand; Hans-Joachim Wunderlich (EURO-DAC, 1990)

Generating pseudo-exhaustive vectors for external testing. - Sybille Hellebrand; Hans-Joachim Wunderlich; Oliver F. Haberl (ITC, 1990)

Synthese vollstaendig testbarer Schaltungen - Sybille Hellebrand (1991)

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. - Sybille Hellebrand; Steffen Tarnick; Bernard Courtois; Janusz Rajski (ITC, 1992)

The pseudoexhaustive test of sequential circuits. - Hans-Joachim Wunderlich; Sybille Hellebrand (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Synthesis of Self-Testable Controllers. - Sybille Hellebrand; Hans-Joachim Wunderlich (EDAC-ETC-EUROASIC, 1994)

An efficient procedure for the synthesis of fast self-testable controller structures. - Sybille Hellebrand; Hans-Joachim Wunderlich (ICCAD, 1994)

Pattern generation for a deterministic BIST scheme. - Sybille Hellebrand; Birgit Reeb; Steffen Tarnick; Hans-Joachim Wunderlich (ICCAD, 1995)

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. - Sybille Hellebrand; Janusz Rajski; Steffen Tarnick; Srikanth Venkataraman; Bernard Courtois (IEEE Trans. Computers, 1995)

STARBIST: Scan Autocorrelated Random Pattern Generation. - Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski; Malgorzata Marek-Sadowska (DAC, 1997)

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. - Vyacheslav N. Yarmolik; Sybille Hellebrand; Hans-Joachim Wunderlich (DATE, 1998)

Fast Self-Recovering Controllers. - Andre Hertwig; Sybille Hellebrand; Hans-Joachim Wunderlich (VTS, 1998)

Synthesizing Fast, Online-Testable Control Units. - Sybille Hellebrand; Hans-Joachim Wunderlich; Andre Hertwig (IEEE Des. Test Comput., 1998)

Mixed-Mode BIST Using Embedded Processors. - Sybille Hellebrand; Hans-Joachim Wunderlich; Andre Hertwig (J. Electron. Test., 1998)

Symmetric Transparent BIST for RAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Vyacheslav N. Yarmolik (DATE, 1999)

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. - Vyacheslav N. Yarmolik; I. V. Bykov; Sybille Hellebrand; Hans-Joachim Wunderlich (EDCC, 1999)

Error Detecting Refreshment for Embedded DRAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets; Vyacheslav N. Yarmolik (VTS, 1999)

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. - Sybille Hellebrand; Huaguo Liang; Hans-Joachim Wunderlich (J. Electron. Test., 2001)

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. - Huaguo Liang; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2002)

A Mixed-Mode BIST Scheme Based on Folding Compression. - Huaguo Liang; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Comput. Sci. Technol., 2002)

Efficient Online and Offline Testing of Embedded DRAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets; Vyacheslav N. Yarmolik (IEEE Trans. Computers, 2002)

A Hybrid Coding Strategy For Optimized Test Data Compression. - Armin Würtenberger; Christofer S. Tautermann; Sybille Hellebrand (ITC, 2003)

Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. - Armin Würtenberger; Christofer S. Tautermann; Sybille Hellebrand (ITC, 2004)

Low power embedded DRAMs with high quality error correcting capabilities. - Philipp Öhler; Sybille Hellebrand (ETS, 2005)

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). - Bernd Becker 001; Ilia Polian; Sybille Hellebrand; Bernd Straube; Hans-Joachim Wunderlich (it Inf. Technol., 2006)

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. - Philipp Öhler; Sybille Hellebrand; Hans-Joachim Wunderlich (DDECS, 2007)

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. - Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym; Bernd Straube (DFT, 2007)

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. - Philipp Öhler; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2007)

An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip. - Muhammad Ali; Michael Welzl; Sven Hessler; Sybille Hellebrand (Int. J. High Perform. Syst. Archit., 2007)

Verification and Analysis of Self-Checking Properties through ATPG. - Marc Hunger; Sybille Hellebrand (IOLTS, 2008)

A Modular Memory BIST for Optimized Memory Repair. - Philipp Öhler; Alberto Bosio; Giorgio Di Natale; Sybille Hellebrand (IOLTS, 2008)

Signature Rollback - A Technique for Testing Robust Circuits. - Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand; Hans-Joachim Wunderlich (VTS, 2008)

Are Robust Circuits Really Robust? - Sybille Hellebrand; Marc Hunger (DFT, 2009)

ATPG-based grading of strong fault-secureness. - Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian; Bernd Becker 001 (IOLTS, 2009)

The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. - Marc Hunger; Sybille Hellebrand (DFT, 2010)

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. - Bernd Becker 001; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren; Hans-Joachim Wunderlich (DSN Workshops, 2010)

Efficient test response compaction for robust BIST using parity sequences. - Thomas Indlekofer; Michael Schnittger; Sybille Hellebrand (ICCD, 2010)

Reusing NoC-infrastructure for test data compression. - Viktor Froese; Rüdiger Ibers; Sybille Hellebrand (VTS, 2010)

Nano-electronic Systems (Nano-elektronische Systeme). - Sybille Hellebrand (it Inf. Technol., 2010)

Diagnostic Test of Robust Circuits. - Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Towards Variation-Aware Test Methods. - Ilia Polian; Bernd Becker 001; Sybille Hellebrand; Hans-Joachim Wunderlich; Peter C. Maxwell (ETS, 2011)

Variation-aware fault modeling. - Fabian Hopsch; Bernd Becker 001; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren; Hans-Joachim Wunderlich (Sci. China Inf. Sci., 2011)

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. - Alejandro Cook; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2012)

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test. - Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz; Hans-Joachim Wunderlich (LATW, 2012)

Analyzing and quantifying fault tolerance properties. - Sybille Hellebrand (LATW, 2013)

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. - Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu 010; Hans-Joachim Wunderlich (ITC, 2014)

Adaptive Bayesian Diagnosis of Intermittent Faults. - Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

SAT-based ATPG beyond stuck-at fault testing. - Sybille Hellebrand; Hans-Joachim Wunderlich (it Inf. Technol., 2014)

Optimized Selection of Frequencies for Faster-Than-at-Speed Test. - Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2015)

A High Performance SEU Tolerant Latch. - Zhengfeng Huang; Huaguo Liang; Sybille Hellebrand (J. Electron. Test., 2015)

X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. - Matthias Kampmann; Sybille Hellebrand (ATS, 2016)

Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. - Matthias Kampmann; Sybille Hellebrand (DDECS, 2017)

Foreword. - Maria K. Michael; Rolf Drechsler; Stephan Eggersglüß; Haralampos-G. D. Stratigopoulos; Sybille Hellebrand; Rob Aitken (ETS, 2017)

Special session on early life failures. - Jyotirmoy V. Deshmukh; Wolfgang Kunz; Hans-Joachim Wunderlich; Sybille Hellebrand (VTS, 2017)

Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. - Chang Liu 010; Eric Schneider; Matthias Kampmann; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2018)

Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. - Alexander Sprenger; Sybille Hellebrand (DDECS, 2018)

Guest Editors' Introduction. - Sybille Hellebrand; Jörg Henkel; Anand Raghunathan; Hans-Joachim Wunderlich (IEEE Embed. Syst. Lett., 2018)

Design for Small Delay Test - A Simulation Study. - Matthias Kampmann; Sybille Hellebrand (Microelectron. Reliab., 2018)

A Hybrid Space Compactor for Adaptive X-Handling. - Mohammad Urf Maaz; Alexander Sprenger; Sybille Hellebrand (ITC, 2019)

Divide and Compact - Stochastic Space Compaction for Faster-than-at-Speed Test. - Alexander Sprenger; Sybille Hellebrand (J. Circuits Syst. Comput., 2019)

Built-In Test for Hidden Delay Faults. - Matthias Kampmann; Michael A. Kochte; Chang Liu 010; Eric Schneider; Sybille Hellebrand; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. - Alexander Sprenger; Somayeh Sadeghi Kohan; Jan Dennis Reimer; Sybille Hellebrand (DFT, 2020)

Logic Fault Diagnosis of Hidden Delay Defects. - Stefan Holst; Matthias Kampmann; Alexander Sprenger; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich; Xiaoqing Wen (ITC, 2020)

Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. - Somayeh Sadeghi Kohan; Sybille Hellebrand (VTS, 2020)

Stress-Aware Periodic Test of Interconnects. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2021)

Optimizing the Streaming of Sensor Data with Approximate Communication. - Somayeh Sadeghi Kohan; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2023)

Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (DSN-W, 2023)

Approximate Communication: Balancing Performance, Power, Reliability, and Safety. - Abdalrhman Badran; Somayeh Sadeghi Kohan; Jan Dennis Reimer; Sybille Hellebrand (ETS, 2023)

Robust Pattern Generation for Small Delay Faults Under Process Variations. - Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Zahra Paria Najafi-Haghi; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (ITC, 2023)

RAPPER: Robust and APProximate ERror Tolerating Communication. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (DFT, 2024)

Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2024)

Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. - Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (ITC, 2024)

Vmin Testing under Variations: Defect vs. Fault Coverage. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (LATS, 2024)

Workload-Aware Periodic Interconnect BIST. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (IEEE Des. Test, 2024)

Robust Pattern Generation for Small Delay Faults under the Impact of Variations. - Hanieh Jafarzadeh; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

Robust DLBIST for Delay Fault Testing: Minimizing PVT Variability with Zero Temperature Coefficient (ZTC) Voltage. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (LATS, 2025)

Zero Overhead Error-Tolerant Communication. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (LATS, 2025)

Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2025)