A Unified Architecture for BCD and Binary Adder/Subtractor. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (DSD, 2011)

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. - P. Sai Phaneendra; Chetan Vudadha; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISCIT, 2011)

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2011)

A Prefix Based Reconfigurable Adder. - Chetan Kumar V.; Sai Phaneendra P.; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISVLSI, 2011)

A Modified Twin Precision Multiplier with 2D Bypassing Technique. - Syed Ershad Ahmed; Sibi Abraham; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2012)

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. - Chetan Vudadha; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (ISVLSI, 2012)

Design of Prefix-Based Optimal Reversible Comparator. - Chetan Vudadha; P. Sai Phaneendra; Sreehari Veeramachaneni; Syed Ershad Ahmed; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (ISVLSI, 2012)

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. - Chetan Vudadha; Goutham Makkena; M. Venkata Swamy Nayudu; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (VLSI Design, 2012)

A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. - Soumya Ganguly; Abhishek Mittal; Syed Ershad Ahmed; M. B. Srinivas (APCCAS, 2014)

A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. - Ch. Santosh Varma; Syed Ershad Ahmed; M. B. Srinivas (VLSID, 2014)

An Iterative Logarithmic Multiplier with Improved Precision. - Syed Ershad Ahmed; Sanket Kadam; M. B. Srinivas (ARITH, 2016)

A Hybrid Energy Efficient Digital Comparator. - Syed Ershad Ahmed; S. Sweekruth Srinivas; M. B. Srinivas (VLSID, 2016)

Improved designs of digit-by-digit decimal multiplier. - Syed Ershad Ahmed; Ch. Santosh Varma; M. B. Srinivas (Integr., 2018)

An Improved Logarithmic Multiplier for Media Processing. - Syed Ershad Ahmed; M. B. Srinivas (J. Signal Process. Syst., 2019)

Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing. - Uppugunduru Anil Kumar; Nishant Jain; Sumit K. Chatterjee; Syed Ershad Ahmed (MIND (2), 2020)

Power-Efficient MLOA for error resilient applications. - Sahith Guturu; Anil Kumar Uppugunduru; Sridhar Thota; Syed Ershad Ahmed (iSES, 2021)

Approximate Multiplier Architectures for Error Resilient Applications. - Uppugunduru Anil Kumar; Ratna Kumari Chintakunta; Sandeep Kumar; K. Jamal; Syed Ershad Ahmed (iSES, 2021)

Lower part OR based Approximate Multiplier for Error Resilient Applications. - Uppugunduru Anil Kumar; Goli Naga Sandesh; Dhoti Ojusteja; Syed Ershad Ahmed (iSES, 2021)

DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications. - Suresh Nambi; Uppugunduru Anil Kumar; Kavya Radhakrishnan; Mythreye Venkatesan; Syed Ershad Ahmed (IEEE Embed. Syst. Lett., 2021)

An Efficient Hardware Approach for Approximate Logarithmic Computation. - Syed Ershad Ahmed; Yerasuri Mohana Sri Krishna (J. Circuits Syst. Comput., 2021)

Compressor based hybrid approximate multiplier architectures with efficient error correction logic. - Anil Kumar Uppugunduru; S. Vignesh Bharadwaj; Syed Ershad Ahmed (Comput. Electr. Eng., 2022)

Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module. - Uppugunduru Anil Kumar; Sumit K. Chatterjee; Syed Ershad Ahmed (IEEE Embed. Syst. Lett., 2022)

A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications. - Uppugunduru Anil Kumar; G. Sahith; Sumit K. Chatterjee; Syed Ershad Ahmed (J. Circuits Syst. Comput., 2022)

Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation. - Uppugunduru Anil Kumar; Sahith Guturu; Syed Ershad Ahmed (Microprocess. Microsystems, 2022)

Design of Energy Efficient Posit Multiplier. - Aditya Anirudh Jonnalagadda; Anil Kumar Uppugunduru; Sreehari Veeramachaneni; Syed Ershad Ahmed (ACM Great Lakes Symposium on VLSI, 2023)

Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications. - Shalini Burri; Gowtham Sri Harsha Kudulla; Pavan Kumar Jogi; Anantha Sai Satwik Vysyaraju; Uppugunduru Anil Kumar; Syed Ershad Ahmed; Sreehari Veeramachaneni (ISED, 2023)

Low Power Approximate Divider and Square Root Circuits for Error Resilient Applications. - Uppugunduru Anil Kumar; Viren Ramchandani; Syed Shakeel Hashmi; Sanjay Dubey; Syed Ershad Ahmed (ISED, 2023)

Low-Power Approximate Multiplier Architecture for Error Resilient Applications. - Apurva Kumari; Ch. Vandana; Chowta Mallikharjuna Rao; Uppugunduru Anil Kumar; Syed Ershad Ahmed (ISED, 2023)

Power Efficient Approximate Ternary Subtractor for Image Processing Applications. - Sangireddy Tharuni; Basani Harshavardhan Reddy; Bhukya Mamatha; Uppugunduru Anil Kumar; Syed Ershad Ahmed; Sreehari Veeramachaneni (iSES, 2023)

Improved approximate multiplier architecture for image processing and neural network applications. - Pramod Alamuri; Uppugunduru Anil Kumar; Vallepu Vannuru; Syed Ershad Ahmed (Microprocess. Microsystems, 2023)

A General Methodology to Optimize Flagged Constant Addition. - Aroondhati Bhure; P. Smriti; Vinay Dhanote; Uppugunduru Anil Kumar; Syed Ershad Ahmed (J. Circuits Syst. Comput., 2023)

Design methodology for highly accurate approximate multipliers for error resilient applications. - Sahith Guturu; Uppugunduru Anil Kumar; S. Vignesh Bharadwaj; Syed Ershad Ahmed (Comput. Electr. Eng., 2023)

CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications. - Uppugunduru Anil Kumar; S. Vignesh Bharadwaj; Avinash Bhat Pattaje; Suresh Nambi; Syed Ershad Ahmed (IEEE Embed. Syst. Lett., 2023)

Energy-Efficient Ternary Multiplier. - Rishi Agrawal; Narayanabhatla Savyasachi Abhijith; Uppugunduru Anil Kumar; Sreehari Veeramachaneni; Syed Ershad Ahmed (AICAS, 2024)

Energy Efficient Approximate Ternary Adder for Image Processing Applications. - Dhananjay Rao Thallikar Shyam; Uppugunduru Anil Kumar; Subham Prasad Dash; Syed Ershad Ahmed (ISED, 2024)

ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks. - Aditya Anirudh Jonnalagadda; Uppugunduru Anil Kumar; Rishi Thotli; Satvik Sardesai; Sreehari Veeramachaneni; Syed Ershad Ahmed (IEEE Access, 2024)

Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders. - Aalelai Vendhan; Syed Ershad Ahmed; S. Gurunarayanan 001 (Circuits Syst. Signal Process., 2024)

HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications. - Sahith Guturu; Uppugunduru Anil Kumar; Shruti Verma; Syed Ershad Ahmed (J. Circuits Syst. Comput., 2024)

Addressing Adversarial Attacks in IoT Using Deep Learning AI Models. - Sesibhushana Rao Bommana; Sreehari Veeramachaneni; Syed Ershad Ahmed; M. B. Srinivas (IEEE Access, 2025)

Design of Approximate Adder With Reconfigurable Accuracy. - Aalelai Vendhan; Syed Ershad Ahmed; S. Gurunarayanan 001 (IEEE Access, 2025)

A Power-Efficient Gaussian Filter Architecture Using Adder Compressors for Edge Detection Application. - Sahith Guturu; Anil Kumar Uppugunduru; Apoorva Sharma; Syed Ershad Ahmed (Circuits Syst. Signal Process., 2025)

Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic. - Aditya Anirudh Jonnalagadda; Rishi Thotli; Sreehari Veeramachaneni; Uppugunduru Anil Kumar; Syed Ershad Ahmed (IEEE Embed. Syst. Lett., 2025)