A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. - Amr Lotfy; Syed Feruz Syed Farooq; Qi S. Wang; Soner Yaldiz; Praveen Mosalikanti; Nasser A. Kurd (CICC, 2015)

19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Amr Elshazly; Nasser A. Kurd (ISSCC, 2016)

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Mark Neidengard; Nasser A. Kurd; Amr Elshazly (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation. - Praveen Mosalikanti; Qi Wang; Kuan-Yueh James Shen; Mark Neidengard; Syed Feruz Syed Farooq; Vaughn Grossnickle; Nasser A. Kurd (ISSCC, 2021)