A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits. - Syed M. Alam; Donald E. Troxel; Carl V. Thompson (ISQED, 2002)

Circuit Level Reliability Analysis of Cu Interconnects. - Syed M. Alam; Chee Lip Gan; Carl V. Thompson; Donald E. Troxel (ISQED, 2004)

Design tool and methodologies for interconnect reliability analysis in integrated circuits. - Syed M. Alam (2004)

Thermal aware cell-based full-chip electromigration reliability analysis. - Syed M. Alam; Donald E. Troxel; Carl V. Thompson (ACM Great Lakes Symposium on VLSI, 2005)

Electromigration Reliability Comparison of Cu and Al Interconnects. - Syed M. Alam; Frank L. Wei; Chee Lip Gan; Carl V. Thompson; Donald E. Troxel (ISQED, 2005)

A 180 Kbit Embeddable MRAM Memory Module. - Joseph J. Nahas; Thomas W. Andre; Chitra K. Subramanian; Hal Lin; Syed M. Alam; Ken Papworth; William L. Martino (CICC, 2007)

Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology. - Syed M. Alam; Robert E. Jones; Shahid Rauf; Ritwik Chatterjee (ISQED, 2007)

Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations. - Syed M. Alam; Chee Lip Gan; Carl V. Thompson; Donald E. Troxel (Microelectron. J., 2007)

Technology, CAD tools, and designs for emerging 3D integration technology. - Syed M. Alam; Mike Ignatowski; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2008)

A Built-In Self-Test Scheme for Soft Error Rate Characterization. - Alodeep Sanyal; Syed M. Alam; Sandip Kundu (IOLTS, 2008)

A 180 Kbit Embeddable MRAM Memory Module. - Joseph J. Nahas; Thomas W. Andre; Brad Garni; Chitra K. Subramanian; Hal Lin; Syed M. Alam; Ken Papworth; William L. Martino (IEEE J. Solid State Circuits, 2008)

Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. - Nauman H. Khan; Syed M. Alam; Soha Hassoun (3DIC, 2009)

System-level comparison of power delivery design for 2D and 3D ICs. - Nauman H. Khan; Syed M. Alam; Soha Hassoun (3DIC, 2009)

Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology. - Syed M. Alam; Robert E. Jones; Scott Pozder; Ankur Jain (ISQED, 2009)

Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis - Karthikeyan Lingasubramanian; Syed M. Alam; Sanjukta Bhanja (CoRR, 2009)

BIST to Detect and Characterize Transient and Parametric Failures. - Alodeep Sanyal; Syed M. Alam; Sandip Kundu (IEEE Des. Test Comput., 2010)

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. - Ioannis Savidis; Syed M. Alam; Ankur Jain; Scott Pozder; Robert E. Jones; Ritwik Chatterjee (Microelectron. J., 2010)

Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration. - Syed M. Alam; Robert E. Jones; Scott Pozder; Ritwik Chatterjee; Shahid Rauf; Ankur Jain (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs. - Nauman H. Khan; Syed M. Alam; Soha Hassoun (ISQED, 2011)

Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures. - Jayita Das; Syed M. Alam; Sanjukta Bhanja (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints. - Ankur Jain; Syed M. Alam; Scott Pozder; Robert E. Jones (IET Comput. Digit. Tech., 2011)

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. - Karthikeyan Lingasubramanian; Syed M. Alam; Sanjukta Bhanja (Microelectron. Reliab., 2011)

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. - Nauman H. Khan; Syed M. Alam; Soha Hassoun (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Non-destructive variability tolerant differential read for non-volatile logic. - Jayita Das; Syed M. Alam; Sanjukta Bhanja (MWSCAS, 2012)

Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture. - Jayita Das; Syed M. Alam; Sanjukta Bhanja (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

ST-MRAM fundamentals, challenges, and applications. - Thomas W. Andre; Syed M. Alam; Dietmar Gogl; C. K. Subramanian; Hal Lin; W. Meadows; X. Zhang; Nicholas D. Rizzo; Jason Janesky; D. Houssameddine; Jon M. Slaughter (CICC, 2013)

Welcome to ISQED 2013. - Mark M. Budnik; Rasit Onur Topaloglu; Pallab Chatterjee; Keith A. Bowman; Kamesh V. Gadepally; Paul Wesling; Syed M. Alam; Rajiv V. Joshi (ISQED, 2013)

Nano Magnetic STT-Logic Partitioning for Optimum Performance. - Jayita Das; Syed M. Alam; Sanjukta Bhanja (IEEE Trans. Very Large Scale Integr. Syst., 2014)

STT-Based Non-Volatile Logic-in-Memory Framework. - Jayita Das; Syed M. Alam; Sanjukta Bhanja (Field-Coupled Nanocomputing, 2014)

Commercialization of 1Gb Standalone Spin-Transfer Torque MRAM. - J. J. Sun; M. DeHerrera; B. Hughes; S. Ikegawa; H. K. Lee; Fred B. Mancoff; K. Nagel; G. Shimon; Syed M. Alam; D. Houssameddine; S. Aggarwal (IMW, 2021)

Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput. - Syed M. Alam; Dimitri Houssameddine; F. Neumeyer; I. Rahman; M. DeHerrera; S. Ikegawa; P. Sanchez; X. Zhang; Y. Wang; J. Williams; Dietmar Gogl; H. Xu; et al. (IMW, 2022)

Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security. - Zachary Kahleifeh; Himanshu Thapliyal; Syed M. Alam (IEEE Trans. Consumer Electron., 2023)

STT-MRAM Antifuse Macro for Memory, SoC, and FPGA Chips. - Syed M. Alam; X. Zhang; H. Xu; M. Sadd; M. DeHerrera; S. Ikegawa; Fred B. Mancoff; K. Nagel; Y. Kim; S. Aggarwal (IMW, 2025)