An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory. - Syed Mohsin Abbas; Soonyoung Lee; Sanghyeon Baeg; Sungju Park (IEEE Trans. Computers, 2014)

Low complexity belief propagation polar code decoder. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (SiPS, 2015)

Low Complexity Belief Propagation Polar Code Decoders. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (CoRR, 2015)

FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. - Zhiliang Qian; Syed Mohsin Abbas; Chi-Ying Tsui (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. - Syed Mohsin Abbas; Chi-Ying Tsui (VLSI-SoC, 2016)

Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO. - Syed Mohsin Abbas; Chi-Ying Tsui (VLSI-SoC (Selected Papers), 2016)

Concatenated LDPC-polar codes decoding through belief propagation. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (ISCAS, 2017)

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High-Throughput VLSI Architecture for GRAND. - Syed Mohsin Abbas; Thibaud Tonnellier; Furkan Ercan; Warren J. Gross (SiPS, 2020)

High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND. - Syed Mohsin Abbas; Thibaud Tonnellier; Furkan Ercan; Marwan Jalaleddine; Warren J. Gross (ICASSP, 2021)

Reduced Complexity RPA Decoder for Reed-Muller Codes. - Jiajie Li 001; Syed Mohsin Abbas; Thibaud Tonnellier; Warren J. Gross (ISTC, 2021)

High-Throughput VLSI Architecture for GRAND Markov Order. - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (SiPS, 2021)

GRAND for Rayleigh Fading Channels. - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (GLOBECOM (Workshops), 2022)

High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. - Syed Mohsin Abbas; Thibaud Tonnellier; Furkan Ercan; Marwan Jalaleddine; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO). - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (J. Signal Process. Syst., 2022)

Step-GRAND: A Low Latency Universal Soft-Input Decoder. - Syed Mohsin Abbas; Chi-Ying Tsui; Marwan Jalaleddine; Warren J. Gross (GLOBECOM (Workshops), 2023)

List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding. - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Confinement Specific Design of SOI Rib Waveguides with Submicron Dimensions and Single Mode Operation. - Abdurrahman Javid Shaikh; Abdul Ghani Abro; Mirza Muhammad Ali Baig; Muhammad Adeel Ahmad Siddiqui; Syed Mohsin Abbas (CoRR, 2024)

Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs. - Mohamed Soliman; Antti Nurmi; Syed Mohsin Abbas (ISCAS, 2025)

Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding. - Syed Mohsin Abbas; Marwan Jalaleddine; Chi-Ying Tsui; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2025)