Design and Synthesis of Self-Checking VLSI Circuits and Systems. - Niraj K. Jha; Sying-Jyan Wang (ICCD, 1991)

Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. - Niraj K. Jha; Sying-Jyan Wang; Phillip C. Gripka (ICCD, 1992)

Design and synthesis of self-checking VLSI circuits. - Niraj K. Jha; Sying-Jyan Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Synthesis of Sequential Machines with Reduced Testing Cost. - Sying-Jyan Wang (EDAC-ETC-EUROASIC, 1994)

Algorithm-Based Fault Tolerance for FFT Networks. - Sying-Jyan Wang; Niraj K. Jha (IEEE Trans. Computers, 1994)

Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. - Po-Ching Hsu; Sying-Jyan Wang (Asian Test Symposium, 1996)

Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing. - Sying-Jyan Wang (J. Parallel Distributed Comput., 1996)

Test and diagnosis of fault logic blocks in FPGAs. - Sying-Jyan Wang; Tsi-Ming Tsai (ICCAD, 1997)

Distributed Routing in a Fault-Tolerant Multistage Interconnection Network. - Sying-Jyan Wang (Inf. Process. Lett., 1997)

Testing and Diagnosis of Interconnect Structures in FPGAs. - Sying-Jyan Wang; Chao-Neng Huang (Asian Test Symposium, 1998)

Efficient built-in self-test algorithm for memory. - Sying-Jyan Wang; Chen-Jung Wei (Asian Test Symposium, 2000)

Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches. - Sying-Jyan Wang; Chia-Chun Lien (J. Inf. Sci. Eng., 2000)

Generating Efficient Tests for Continuous Scan. - Sying-Jyan Wang; Sheng-Nan Chiou (DAC, 2001)

Distributed Diagnosis in Multistage Interconnection Networks. - Sying-Jyan Wang (J. Parallel Distributed Comput., 2001)

A Reseeding Technique for LFSR-Based BIST Applications. - Nan-Cheng Li; Sying-Jyan Wang (Asian Test Symposium, 2002)

Retiming-based logic synthesis for low-power. - Yu-Lung Hsu; Sying-Jyan Wang (ISLPED, 2002)

Low Power BIST with Smoother and Scan-Chain Reorder . - Nan-Cheng Lai; Sying-Jyan Wang; Yu-Hsuan Fu (Asian Test Symposium, 2004)

Test Data Compression with Partial LFSR-Reseeding. - Yu-Hsuan Fu; Sying-Jyan Wang (Asian Test Symposium, 2005)

Low power parallel multiplier with column bypassing. - Mingchen Wen; Sying-Jyan Wang; Yen-Nan Lin (ISCAS (2), 2005)

FSM-based programmable memory BIST with macro command. - Po-Chang Tsai; Sying-Jyan Wang; Feng-Ming Chang (MTDT, 2005)

Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. - Sying-Jyan Wang; Kuo-Lin Peng; Katherine Shu-Min Li (ATS, 2006)

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. - Nan-Cheng Lai; Sying-Jyan Wang; Y.-H. Fu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs. - Nan-Cheng Lai; Sying-Jyan Wang (ATS, 2007)

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis. - Sying-Jyan Wang; Xin-Long Li; Katherine Shu-Min Li (ATS, 2007)

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. - Sying-Jyan Wang; Po-Chang Tsai; Hung-Ming Weng; Katherine Shu-Min Li (ATS, 2007)

High-level test synthesis for delay fault testability. - Sying-Jyan Wang; Tung-Hua Yeh (DATE, 2007)

Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. - Sying-Jyan Wang; Yan-Ting Chen; Katherine Shu-Min Li (ISCAS, 2007)

Test Data Compression for Minimum Test Application Time. - Po-Chang Tsai; Sying-Jyan Wang; Ching-Hung Lin; Tung-Hua Yeh (J. Inf. Sci. Eng., 2007)

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests. - Nan-Cheng Lai; Sying-Jyan Wang (ATS, 2008)

Design and analysis of skewed-distribution scan chain partition for improved test data compression. - Sying-Jyan Wang; Shih-Cheng Chen; Katherine Shu-Min Li (ISCAS, 2008)

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction. - Po-Chang Tsai; Sying-Jyan Wang (IET Comput. Digit. Tech., 2008)

Layout-aware scan chain reorder for launch-off-shift transition test coverage. - Sying-Jyan Wang; Kuo-Lin Peng; Kuang-Cyun Hsiao; Katherine Shu-Min Li (ACM Trans. Design Autom. Electr. Syst., 2008)

Level Converting Scan Flip-flops. - Katherine Shu-Min Li; Ming-Hua Hsieh; Sying-Jyan Wang (ISCAS, 2009)

Low Peak Power ATPG for n-Detection Test. - Sying-Jyan Wang; Kuo-Lin Fu; Katherine Shu-Min Li (ISCAS, 2009)

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint. - Sying-Jyan Wang; Katherine Shu-Min Li; Shih-Cheng Chen; Huai-Yan Shiu; Yun-Lung Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. - Sying-Jyan Wang; Tung-Hua Yeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Thermal Safe High Level Test Synthesis for Hierarchical Testability. - Tung-Hua Yeh; Sying-Jyan Wang (Asian Test Symposium, 2010)

De Bruijn graph-based communication modeling for fault tolerance in smart grids. - Bo-Chuan Cheng; Katherine Shu-Min Li; Sying-Jyan Wang (APCCAS, 2012)

Low-power delay test architecture for pre-bond test. - Sying-Jyan Wang; Han-Hsuan Hsu; Katherine Shu-Min Li (ISCAS, 2012)

Power-Aware High-Level Synthesis With Clock Skew Management. - Tung-Hua Yeh; Sying-Jyan Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator. - Yingchieh Ho; Katherine Shu-Min Li; Sying-Jyan Wang (Asian Test Symposium, 2013)

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. - Katherine Shu-Min Li; Cheng-You Ho; Ruei-Ting Gu; Sying-Jyan Wang; Yingchieh Ho; Jiun-Jie Huang; Bo-Chuan Cheng; An-Ting Liu (Asian Test Symposium, 2013)

Synthesis of 3D clock tree with pre-bond testability. - Sying-Jyan Wang; Cheng-Hao Lin; Katherine Shu-Min Li (ISCAS, 2013)

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process. - Yingchieh Ho; Katherine Shu-Min Li; Sying-Jyan Wang (VLSI-DAT, 2013)

Low-cost testing of TSVs in 3D stacks with pre-bond testable dies. - Sying-Jyan Wang; Yu-Siao Chen; Katherine Shu-Min Li (VLSI-DAT, 2013)

Delay Test with Embedded Test Pattern Generator. - Nan-Cheng Lai; Sying-Jyan Wang (J. Inf. Sci. Eng., 2013)

Optimized Pre-bond Test Methodology for Silicon Interposer Testing. - Katherine Shu-Min Li; Sying-Jyan Wang; Jia-Lin Wu; Cheng-You Ho; Yingchieh Ho; Ruei-Ting Gu; Bo-Chuan Cheng (ATS, 2014)

Improving Output Compaction Efficiency with High Observability Scan Chains. - Sying-Jyan Wang; Che-Wei Kao; Katherine Shu-Min Li (ATS, 2014)

Fast and accurate statistical static timing analysis. - Sying-Jyan Wang; Tsung-Huei Tzeng; Katherine Shu-Min Li (ISCAS, 2014)

Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. - Jain-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ASP-DAC, 2016)

Side-Channel Attack on Flipped Scan Chains. - Sying-Jyan Wang; Ting-Jui Choi; Katherine Shu-Min Li (ATS, 2016)

Test generation for combinational hardware Trojans. - Sying-Jyan Wang; Jhih-Yu Wei; Shih-Heng Huang; Katherine Shu-Min Li (AsianHOST, 2016)

Test and diagnosis of paper-based microfluidic biochips. - Jain-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (VTS, 2016)

Testing Clock Distribution Networks. - Sying-Jyan Wang; Hsiang-Hsueh Chen; Chin-Hung Lien; Katherine Shu-Min Li (ATS, 2017)

Design-for-testability for paper-based digital microfluidic biochips. - Jain-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (DFT, 2017)

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. - Katherine Shu-Min Li; Sying-Jyan Wang; Ruei-Ting Gu; Bo-Chuan Cheng (IEEE Des. Test, 2017)

Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip. - Katherine Shu-Min Li; Sying-Jyan Wang (ACM Trans. Design Autom. Electr. Syst., 2017)

Digital Rights Management for Paper-Based Microfluidic Biochips. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ATS, 2018)

Register PUF with No Power-Up Restrictions. - Sying-Jyan Wang; Chin-Hung Lien; Katherine Shu-Min Li (ISCAS, 2018)

SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips. - Jia-Lin Wu; Katherine Shu-Min Li; Jain-De Li; Sying-Jyan Wang; Tsung-Yi Ho (VLSI-DAT, 2018)

Adversarial Attack against Modeling Attack on PUFs. - Sying-Jyan Wang; Yu-Shen Chen; Katherine Shu-Min Li (DAC, 2019)

TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. - Andrew Yi-Ann Huang; Katherine Shu-Min Li; Cheng-Yen Tsai; Ken Chau-Cheung Cheng; Sying-Jyan Wang; Xu-Hao Jiang; Leon Chou; Chen-Shiun Lee (ITC, 2019)

Exploiting distribution of unknown values in test responses to optimize test output compactors. - Sying-Jyan Wang; Kuan-Ting Yeh; Katherine Shu-Min Li (Integr., 2019)

Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. - Jian-De Li; Chun-Hao Kuo; Guan-Ruei Lu; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho; Hung-Ming Chen; Shiyan Hu 001 (Microelectron. J., 2019)

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Andrew Yi-Ann Huang; Ji-Wei Li; Leon Li-Yang Chen; Nova Cheng-Yen Tsai; Sying-Jyan Wang; Chen-Shiun Lee; Leon Chou; Peter Yi-Yu Liao; Hsing-Chung Liang; Jwu E. Chen (DATE, 2020)

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. - Katherine Shu-Min Li; Peter Yi-Yu Liao; Leon Chou; Ken Chau-Cheung Cheng; Andrew Yi-Ann Huang; Sying-Jyan Wang; Gus Chang-Hung Han (ETS, 2020)

Feature Selection for Malicious Traffic Detection with Machine Learning. - Sying-Jyan Wang; Cheng Xuan Cai; Yen-Wen Tseng; Katherine Shu-Min Li (ICS, 2020)

Watermarking for Paper-Based Digital Microfluidic Biochips. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ITC-Asia, 2020)

TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. - Leon Li-Yang Chen; Katherine Shu-Min Li; Ken Chau-Cheung Cheng; Sying-Jyan Wang; Andrew Yi-Ann Huang; Leon Chou; Nova Cheng-Yen Tsai; Chen-Shiun Lee (ITC, 2020)

Innovative Practice on Wafer Test Innovations. - Dyi-Chung Hu; Hirohito Hashimoto; Li-Fong Tseng; Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Sying-Jyan Wang; Sean Y.-S. Chen; Jwu E. Chen; Clark Liu; Andrew Yi-Ann Huang (VTS, 2020)

Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. - Fang-Chi Wu; Jian-De Li; Katherine Shu-Min Li; Sying-Jyan Wang; Tsung-Yi Ho (DATE, 2021)

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. - Katherine Shu-Min Li; Leon Li-Yang Chen; Ken Chau-Cheung Cheng; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Nova Cheng-Yen Tsai; Leon Chou; Gus Chang-Hung Han; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ETS, 2021)

Integrated Scratch Marker for Wafer Defect Diagnosis. - Katherine Shu-Min Li; Leon Li-Yang Chen; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Ken Chau-Cheung Cheng (ITC-Asia, 2021)

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. - Leon Li-Yang Chen; Katherine Shu-Min Li; Xu-Hao Jiang; Sying-Jyan Wang; Andrew Yi-Ann Huang; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ITC, 2021)

WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. - Peter Yi-Yu Liao; Katherine Shu-Min Li; Leon Li-Yang Chen; Sying-Jyan Wang; Andrew Yi-Ann Huang; Ken Chau-Cheung Cheng; Nova Cheng-Yen Tsai; Leon Chou (ITC, 2021)

Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs. - Sying-Jyan Wang; Tzu-Heng Chang; Katherine Shu-Min Li (VLSI-DAT, 2021)

Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning. - Sying-Jyan Wang; Yu-Sheng Chen; Katherine Shu-Min Li (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ASP-DAC, 2022)

Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication. - Sying-Jyan Wang; Katherine Shu-Min Li; Chen-Yeh Lin; Song-Kong Chong (ATS, 2022)

Trojan Insertions of Fully Programmable Valve Arrays. - Nadun Sinhabahu; Jian-De Li; Katherine Shu-Min Li; Sying-Jyan Wang; Tsung-Yi Ho (ETS, 2022)

Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Sying-Jyan Wang; Andrew Yi-Ann Huang; Chen-Shiun Lee; Leon Li-Yang Chen; Peter Yi-Yu Liao; Nova Cheng-Yen Tsai (ITC, 2022)

Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. - Nadun Sinhabahu; Katherine Shu-Min Li; Jian-De Li; J. R. Wang; Sying-Jyan Wang (ITC, 2022)

Improving IJTAG Test Efficiency and Security. - Sying-Jyan Wang; Yen-Chang Shih; Katherine Shu-Min Li; Chen-Yeh Lin; Song-Kong Chong (VLSI-DAT, 2022)

Implementing OIML R46 Communication Unit for DLMS/COSEM Security Suite 1 and Passing CTT V3.1 Test. - Chun-Tsai Chien; Chien-Lung Wang; I-En Liao; Sying-Jyan Wang (ICNSC, 2023)

Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. - Nadun Sinhabahu; Katherine Shu-Min Li; Sying-Jyan Wang; J. R. Wang; Matt Ho (ITC, 2023)

Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (Integr., 2023)

Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ACM Trans. Design Autom. Electr. Syst., 2024)

Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. - Katherine Shu-Min Li; Fang-Chi Wu; Jian-De Li; Sying-Jyan Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Masking Based Protection Mechanism for Ascon against CPA Attack. - Sying-Jyan Wang; Ho Lam Cheung; Katherine Shu-Min Li (ISCAS, 2025)

Design of Reliable and Modeling-Attack Resistant Strong PUFs for Lightweight Applications. - Sying-Jyan Wang; Gong-Chi Wang; Chi-Yun Chen; Katherine Shu-Min Li (ISCAS, 2025)