Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs. - Kiichi Tachi; Sylvain Barraud; Kuniyuki Kakushima; Hiroshi Iwai; Sorin Cristoloveanu; Thomas Ernst 005 (Microelectron. Reliab., 2011)

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. - Veeresh Deshpande; Sylvain Barraud; Xavier Jehl; Romain Wacquez; Maud Vinet; Remi Coquand; B. Roche; B. Voisin; François Triozon; C. Vizioz; L. Tosti; Bernard Previtali; et al. (ESSDERC, 2012)

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. - Masahiro Koyama; Mikaël Cassé; Remi Coquand; Sylvain Barraud; Hiroshi Iwai; Gérard Ghibaudo; Gilles Reimbold (ESSDERC, 2012)

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. - Remi Coquand; Sylvain Barraud; Mikaël Cassé; Masahiro Koyama; Virginie Maffini-Alvaro; Marie-Pierre Samson; Lucie Tosti; Xavier Mescot; Gérard Ghibaudo; Stéphane Monfray; Frédéric Boeuf; Olivier Faynot; et al. (ESSDERC, 2013)

Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. - Masahiro Koyama; Mikaël Cassé; Remi Coquand; Sylvain Barraud; Gérard Ghibaudo; Hiroshi Iwai; Gilles Reimbold (ESSDERC, 2013)

Back-gate effects and detailed characterization of junctionless transistor. - Mukta Singh Parihar; Fanyu Liu; Carlos Navarro; Sylvain Barraud; Maryline Bawedin; Irina Ionica; Abhinav Kranti; Sorin Cristoloveanu (ESSDERC, 2015)

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model. - J. Pelloux-Prayer; Mikaël Cassé; François Triozon; Sylvain Barraud; Yann-Michel Niquet; J.-L. Rouviere; Olivier Faynot; Gilles Reimbold (ESSDERC, 2015)

Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs. - R. Lavieville; Theano A. Karatsori; Christoforos G. Theodorou; Sylvain Barraud; C. A. Dimitriadis; Gérard Ghibaudo (ESSDERC, 2016)

Analog performance of strained SOI nanowires down to 10K. - Bruna Cardoso Paz; Marcelo Antonio Pavanello; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot (ESSDERC, 2016)

Drain current model for short-channel triple gate junctionless nanowire transistors. - Bruna Cardoso Paz; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Olivier Faynot; F. Avila-Herrera; Antonio Cerdeira; Marcelo Antonio Pavanello (Microelectron. Reliab., 2016)

A new method for junctionless transistors parameters extraction. - Renan Trevisoli Doria; Rodrigo Trevisoli Doria; Michelly de Souza; Marcelo Antonio Pavanello; Sylvain Barraud (ESSDERC, 2017)

SOI CMOS technology for quantum information processing. - Louis Hutin; Benoit Bertrand; Romain Maurand; Matias Urdampilleta; Baptiste Jadot; Heorhii Bohuslavskyi; L. Bourdet; Yann-Michel Niquet; Xavier Jehl; Sylvain Barraud; C. Bauerle; Tristan Meunier; et al. (ICICDT, 2017)

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. - Bruna Cardoso Paz; Renan Trevisoli Doria; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (Microelectron. Reliab., 2017)

Towards scalable silicon quantum computing. - Maud Vinet; Louis Hutin; Benoit Bertrand; Heorhii Bohuslavskyi; Andrea Corna; Anthony Amisse; Alessandro Crippa; Léo Bourdet; Romain Maurand; Sylvain Barraud; Matias Urdampilleta; Christopher Bäuerle; et al. (DRC, 2018)

Si MOS technology for spin-based quantum computing. - Louis Hutin; Benoit Bertrand; Romain Maurand; Alessandro Crippa; Matias Urdampilleta; Y. J. Kim; A. Amisse; Heorhii Bohuslavskyi; L. Bourdet; Sylvain Barraud; Xavier Jehl; Yann-Michel Niquet; et al. (ESSDERC, 2018)

Performance & reliability of 3D architectures (πfet, Finfet, Ωfet). - Antoine Laurent; Xavier Garros; Sylvain Barraud; J. Pelloux-Prayer; Mikaël Cassé; Fred Gaillard; X. Federspiel; David Roy 001; E. Vincent; Gérard Ghibaudo (IRPS, 2018)

Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors. - Renan Trevisoli; Rodrigo Trevisoli Doria; Sylvain Barraud; Marcelo Antonio Pavanello (ESSDERC, 2019)

Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. - Mona Ezzadeen; D. Bosch; Bastien Giraud; Sylvain Barraud; Jean-Philippe Noël; Didier Lattard; Joris Lacord; Jean-Michel Portal; François Andrieu (CoRR, 2020)

Wafer-scale fabrication of biologically sensitive Si nanowire FET: from pH sensing to electrical detection of DNA hybridization. - R. Midahuen; Bernard Previtali; C. Fontelaye; G. Nonglaton; V. Stambouli; Sylvain Barraud (ESSDERC, 2021)

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. - Michelly de Souza; Sylvain Barraud; Mikaël Cassé; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (ESSDERC, 2021)

A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing. - T. Dubreuil; P. Amari; Sylvain Barraud; Joris Lacord; Eduardo Esmanhotto; Valentina Meli; S. Martin; Niccolo Castellani; Bernard Previtali; François Andrieu (IMW, 2022)

Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory. - T. Dubreuil; Sylvain Barraud; J.-M. Pedini; Jean-Michel Hartmann; F. Boulard; A. Sarrazin; A. Gharbi; Johannes Sturm; A. Lambert; S. Martin; Niccolo Castellani; A. Anotta; et al. (ESSDERC, 2023)

Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals. - Ancelin Salerno; Sylvain Barraud (ICCAD, 2024)

Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires. - Giovanni Almeida Matos; Jaime CalÇade Rodrigues; Michelly de Souza; Mikaël Cassé; Sylvain Barraud; Olivier Faynot; Marcelo Antonio Pavanello (CCE, 2024)

Novel and Efficient Hyperdimensional Encoding of Surface Electromyography Signals for Hand Gesture Recognition. - Ancelin Salerno; Sylvain Barraud (BIOSTEC (1), 2025)

Compact MEOL OxRAM with 14 Conductance Levels for Dense Embedded Inference Computing. - J. Minguet Lopez; Sylvain Barraud; Manon Dampfhoffer; Aurelie Souhaité; T. Dubreuil; J.-M. Pedini; C. Comboroure; A. Gharbi; F. Boulard; C. Castan; A. Lambert; François Andrieu (IRPS, 2025)