Continuous representation of the performance of a CMOS library. - B. Lasbouygues; Joel Schindler; Sylvain Engels; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ESSCIRC, 2003)

Statistical Characterization of Library Timing Performance. - Vincent Migairou; Robin Wilson; Sylvain Engels; Nadine Azémard; Philippe Maurine (PATMOS, 2006)

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. - Sylvain Engels; Robin Wilson; Nadine Azémard; Philippe Maurine (Integr., 2006)

Logical effort model extension to propagation delay representation. - B. Lasbouygues; Sylvain Engels; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. - Vincent Migairou; Robin Wilson; Sylvain Engels; Zeqin Wu; Nadine Azémard; Philippe Maurine (PATMOS, 2007)

Product On-Chip Process Compensation for Low Power and Yield Enhancement. - Nabila Moubdi; Philippe Maurine; Robin Wilson; Nadine Azémard; Vincent Dumettier; Abhishek Bansal 003; Sebastien Barasinski; Alain Tournier; Guy Durieu; David Meyer; Pierre Busson; Sarah Verhaeren; et al. (PATMOS, 2009)

Timing margin evaluation with a simple statistical timing analysis flow. - Vincent Migairou; Robin Wilson; Sylvain Engels; Zeqin Wu; Nadine Azémard; Philippe Maurine (J. Embed. Comput., 2009)

On-Chip Process Variability Monitoring Flow. - Nabila Moubdi; Philippe Maurine; Robin Wilson; Sylvain Engels; Nadine Azémard; Vincent Dumettier; Pierre Busson (J. Low Power Electron., 2010)

Bottom-up digital system-level reliability modeling. - N. Ruiz Amador; Vincent Huard; E. Pion; Florian Cacho; Damien Croain; V. Robert; Sylvain Engels; Philippe Flatresse; Lorena Anghel (CICC, 2011)

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. - Julien Le Coz; Philippe Flatresse; Sylvain Engels; Alexandre Valentian; Marc Belleville; Christine Raynaud; Damien Croain; Pascal Urard (ISSCC, 2011)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. - Edith Beigné; Ivan Miro-Panades; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Farhat Thabet; Benoît Tain; K. Benchehida; Sylvain Engels; Robin Wilson; et al. (ESSCIRC, 2013)

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. - Philippe Flatresse; Bastien Giraud; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Fabien Giner; Deepak-Kumar Arora; Franck Arnaud; Nicolas Planes; Julien Le Coz; Olivier Thomas; Sylvain Engels; Giorgio Cesana; et al. (ISSCC, 2013)

Clockless Design Performance Monitoring for Nanometer Technologies. - Marc Renaudin; Aurélien Buhrig; Charles Guillemet; Robin Wilson; Sylvain Engels (ASYNC, 2014)

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. - Ivan Miro Panades; Edith Beigné; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Anca Molnos; Farhat Thabet; Benoît Tain; Karim Ben Chehida; Sylvain Engels; et al. (IEEE J. Solid State Circuits, 2014)

Event-based design strategy for circuit electromagnetic compatibility. - Sophie Germain; Sylvain Engels; Laurent Fesquet (EBCCSP, 2017)

A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. - Sophie Germain; Sylvain Engels; Laurent Fesquet (ASYNC, 2018)

A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. - Marc Renaudin; Aymane Bouzafour; Sylvain Engels; Robin Wilson (J. Low Power Electron., 2018)

An Event-Based Strategy for ASK demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (EBCCSP, 2019)

A Distributed Body-Biasing Strategy for Asynchronous Circuits. - Laurent Fesquet; Yoan Decoudu; Alexis Rodrigo Iga Jadue; Thiago Ferreira de Paiva Leite; Otto Aureliano Rolloff; M. Diallo; Rodrigo Possamai Bastos; Katell Morin-Allory; Sylvain Engels (VLSI-SoC, 2019)

A Digital Event-Based Strategy for ASK demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (VLSI-SoC, 2019)

Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (EBCCSP, 2021)

A Novel Event-Based Method for ASK Demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (LASCAS, 2022)

Method for Data-Driven Pruning in Micropipeline Circuits. - Cristiano Merio; Xavier Lesage; Ali Naimi; Sylvain Engels; Katell Morin-Allory; Laurent Fesquet (VLSI-SoC, 2023)

Data-driven Processing Element for Sparse Convolutional Neural Networks. - Xavier Lesage; Cristiano Merio; Fernando Welzel; Luca Sauer de Araujo; Sylvain Engels; Laurent Fesquet (NewCAS, 2024)

Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits. - Jéssica Gonsalves Santos; Ismael de Almeida Junior; Sylvain Engels; Robin Wilson; Laurent Fesquet (SBCCI, 2025)