Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. - Szu-Pang Mu; Yi-Ming Wang; Hao-Yu Yang; Mango Chia-Tso Chao; Shi-Hao Chen; Chih-Mou Tseng; Tsung-Ying Tsai (ICCAD, 2010)

Theoretical analysis for low-power test decompression using test-slice duplication. - Szu-Pang Mu; Mango Chia-Tso Chao (VTS, 2010)

Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax. - Szu-Pang Mu; Wen-Hsiang Chang; Mango C.-T. Chao; Yi-Ming Wang; Ming-Tung Chang; Min-Hsiu Tsai (ICCAD, 2016)

Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators. - Szu-Pang Mu; Mango C.-T. Chao; Shi-Hao Chen; Yi-Ming Wang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique. - Wen-Hsiang Chang; Chien-Hsueh Lin; Szu-Pang Mu; Li-De Chen; Cheng-Hong Tsai; Yen-Chih Chiu; Mango C.-T. Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

DVFS Binning Using Machine-Learning Techniques. - Keng-Wei Chang; Chun-Yang Huang; Szu-Pang Mu; Jian-Min Huang; Shi-Hao Chen; Mango C.-T. Chao (ITC-Asia, 2018)