Power model analysis using variable rate clock network in CMOS processor. - T. Joby Titus; V. Vijayakumari; B. Saranya; V. S. Sanjana Devi (ICCCNT, 2016)

Clock node capacity minimization using lookup table based controller for ultrasound and medical imaging processor. - T. Joby Titus; V. Vijayakumari (Clust. Comput., 2019)

Technical Study on 5G Using Soft Computing Methods. - J. Divakaran; Somashekhar Malipatil; Tareeq Zaid; M. Pushpalatha; Vilaskumar M. Patil; Arvind Chakrapani; T. Joby Titus; Kannan Srihari; M. Ragul Vignesh; Baswaraj Gadgay; Venkatesa Prabhu Sundramurthy (Sci. Program., 2022)