An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. - T. K. Priya; K. Sridharan 001 (VLSI Design, 2004)

A parallel algorithm for constructing reduced visibility graph and its FPGA implementation. - K. Sridharan 001; T. K. Priya (J. Syst. Archit., 2004)

The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation. - K. Sridharan 001; T. K. Priya (IEEE Trans. Ind. Electron., 2005)

A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. - T. K. Priya; P. Rajesh Kumar; K. Sridharan 001 (Microprocess. Microsystems, 2006)

A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. - T. K. Priya; K. Sridharan 001 (Microprocess. Microsystems, 2006)

A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations. - K. Sridharan 001; T. K. Priya (IEEE Trans. Ind. Electron., 2007)