The anatomy of the register file in a multiscalar processor. - Scott E. Breach; T. N. Vijaykumar; Gurindar S. Sohi (MICRO, 1994)

Multiscalar Processors. - Gurindar S. Sohi; Scott E. Breach; T. N. Vijaykumar (ISCA, 1995)

Dynamic Speculation and Synchronization of Data Dependences. - Andreas Moshovos; Scott E. Breach; T. N. Vijaykumar; Gurindar S. Sohi (ISCA, 1997)

Task Selection for a Multiscalar Processor. - T. N. Vijaykumar; Gurindar S. Sohi (MICRO, 1998)

Is SC + ILP=RC? - Chris Gniady; Babak Falsafi; T. N. Vijaykumar (ISCA, 1999)

Task Selection for the Multiscalar Architecture. - T. N. Vijaykumar; Gurindar S. Sohi (J. Parallel Distributed Comput., 1999)

Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories - Michael D. Powell; Se-Hyun Yang; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (ISLPED, 2000)

Reactive-Associative Caches. - Brannon Batson; T. N. Vijaykumar (IEEE PACT, 2001)

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. - Se-Hyun Yang; Michael D. Powell; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (HPCA, 2001)

Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor. - Chong-liang Ooi; Seon Wook Kim; Il Park 001; Rudolf Eigenmann; Babak Falsafi; T. N. Vijaykumar (ICS, 2001)

Skipper: a microarchitecture for exploiting control-flow independence. - Chen-Yong Cher; T. N. Vijaykumar (MICRO, 2001)

Reducing set-associative cache energy via way-prediction and selective direct-mapping. - Michael D. Powell; Amit Agarwal 001; T. N. Vijaykumar; Babak Falsafi; Kaushik Roy 001 (MICRO, 2001)

Reference idempotency analysis: a framework for optimizing speculative execution. - Seon Wook Kim; Chong-liang Ooi; Rudolf Eigenmann; Babak Falsafi; T. N. Vijaykumar (PPoPP, 2001)

Speculative Versioning Cache. - T. N. Vijaykumar; Sridhar Gopal; James E. Smith 001; Gurindar S. Sohi (IEEE Trans. Parallel Distributed Syst., 2001)

Reducing leakage in a high-performance deep-submicron instruction cache. - Michael D. Powell; Se-Hyun Yang; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. - Se-Hyun Yang; Michael D. Powell; Babak Falsafi; T. N. Vijaykumar (HPCA, 2002)

Transient-Fault Recovery Using Simultaneous Multithreading. - T. N. Vijaykumar; Irith Pomeranz; Karl Cheng (ISCA, 2002)

Reducing register ports for higher speed and lower energy. - Il Park 001; Michael D. Powell; T. N. Vijaykumar (MICRO, 2002)

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. - Amit Agarwal 001; Kaushik Roy 001; T. N. Vijaykumar (Embedded Software for SoC, 2003)

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. - Amit Agarwal 001; Kaushik Roy 001; T. N. Vijaykumar (DATE, 2003)

Deterministic Clock Gating for Microprocessor Power Reduction. - Hai Li 001; Swarup Bhunia; Yiran Chen 001; T. N. Vijaykumar; Kaushik Roy 001 (HPCA, 2003)

Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. - Jahangir Hasan; Satish Chandra 001; T. N. Vijaykumar (ISCA, 2003)

Iimplicitly-Multithreaded Processors. - Il Park 001; Babak Falsafi; T. N. Vijaykumar (ISCA, 2003)

Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. - Michael D. Powell; T. N. Vijaykumar (ISCA, 2003)

Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. - Michael D. Powell; T. N. Vijaykumar (ISLPED, 2003)

Accelerating private-key cryptography via multithreading on symmetric multiprocessors. - Praveen Dongara; T. N. Vijaykumar (ISPASS, 2003)

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. - Zeshan Chishti; Michael D. Powell; T. N. Vijaykumar (MICRO, 2003)

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. - Hai Li 001; Chen-Yong Cher; T. N. Vijaykumar; Kaushik Roy 001 (MICRO, 2003)

Reducing Design Complexity of the Load/Store Queue. - Il Park 001; Chong-liang Ooi; T. N. Vijaykumar (MICRO, 2003)

Transient-Fault Recovery for Chip Multiprocessors. - Mohamed A. Gomaa; Chad Scarbrough; T. N. Vijaykumar; Irith Pomeranz (IEEE Micro, 2003)

Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. - Chen-Yong Cher; Antony L. Hosking; T. N. Vijaykumar (ASPLOS, 2004)

Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. - Mohamed A. Gomaa; Michael D. Powell; T. N. Vijaykumar (ASPLOS, 2004)

Exploiting Resonant Behavior to Reduce Inductive Noise. - Michael D. Powell; T. N. Vijaykumar (ISCA, 2004)

Wire Delay is Not a Problem for SMT (In the Near Future). - T. N. Vijaykumar; Zeshan Chishti (ISCA, 2004)

Min-cut program decomposition for thread-level speculation. - Troy A. Johnson; Rudolf Eigenmann; T. N. Vijaykumar (PLDI, 2004)

DCG: deterministic clock-gating for low-power microprocessor design. - Hai Li 001; Swarup Bhunia; Yiran Chen 001; Kaushik Roy 001; T. N. Vijaykumar (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Heat Stroke: Power-Density-Based Denial of Service in SMT. - Jahangir Hasan; Ankit Jalote; T. N. Vijaykumar; Carla E. Brodley (HPCA, 2005)

Optimizing Replication, Communication, and Capacity Allocation in CMPs. - Zeshan Chishti; Michael D. Powell; T. N. Vijaykumar (ISCA, 2005)

Rescue: A Microarchitecture for Testability and Defect Tolerance. - Ethan Schuchman; T. N. Vijaykumar (ISCA, 2005)

Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. - Michael D. Powell; Ethan Schuchman; T. N. Vijaykumar (MICRO, 2005)

Dynamic pipelining: making IP-lookup truly scalable. - Jahangir Hasan; T. N. Vijaykumar (SIGCOMM, 2005)

Detection and prevention of stack buffer overflow attacks. - Benjamin A. Kuperman; Carla E. Brodley; Hilmi Ozdoganoglu; T. N. Vijaykumar; Ankit Jalote (Commun. ACM, 2005)

Combined circuit and architectural level variable supply-voltage scaling for low power. - Hai Li 001; Chen-Yong Cher; Kaushik Roy 001; T. N. Vijaykumar (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. - Chen-Yong Cher; Il Park 001; T. N. Vijaykumar (ARCS, 2006)

A program transformation and architecture support for quantum uncomputation. - Ethan Schuchman; T. N. Vijaykumar (ASPLOS, 2006)

Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. - Jin-Yi Wang; Yen-Shiang Shue; T. N. Vijaykumar; Saurabh Bagchi (ICCD, 2006)

Dynamic feature selection for hardware prediction. - Alan Fern; Robert Givan; Babak Falsafi; T. N. Vijaykumar (J. Syst. Archit., 2006)

Opportunistic Transient-Fault Detection. - Mohamed A. Gomaa; T. N. Vijaykumar (IEEE Micro, 2006)

SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address. - Hilmi Ozdoganoglu; T. N. Vijaykumar; Carla E. Brodley; Benjamin A. Kuperman; Ankit Jalote (IEEE Trans. Computers, 2006)

Exploiting reference idempotency to reduce speculative storage overflow. - Seon Wook Kim; Chong-liang Ooi; Rudolf Eigenmann; Babak Falsafi; T. N. Vijaykumar (ACM Trans. Program. Lang. Syst., 2006)

BlackJack: Hard Error Detection with Redundant Threads on SMT. - Ethan Schuchman; T. N. Vijaykumar (DSN, 2007)

Aquacore: a programmable architecture for microfluidics. - Ahmed M. Amin; Mithuna Thottethodi; T. N. Vijaykumar; Steven Wereley; Stephen C. Jacobson (ISCA, 2007)

Resource area dilation to reduce power density in throughput servers. - Michael D. Powell; T. N. Vijaykumar (ISLPED, 2007)

Speculative thread decomposition through empirical optimization. - Troy A. Johnson; Rudolf Eigenmann; T. N. Vijaykumar (PPoPP, 2007)

Shapeshifter: Dynamically changing pipeline width and speed to address process variations. - Eric Chun; Zeshan Chishti; T. N. Vijaykumar (MICRO, 2008)

Automatic volume management for programmable microfluidics. - Ahmed M. Amin; Mithuna Thottethodi; T. N. Vijaykumar; Steven Wereley; Stephen C. Jacobson (PLDI, 2008)

Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. - Zeshan Chishti; T. N. Vijaykumar (IEEE Trans. Computers, 2008)

Speculatively Multithreaded Architectures. - Gurindar S. Sohi; T. N. Vijaykumar (Multicore Processors and Systems, 2009)

Joint optimization of idle and cooling power in data centers while maintaining response time. - Faraz Ahmad; T. N. Vijaykumar (ASPLOS, 2010)

LiteTM: Reducing transactional state overhead. - Syed Ali Raza Jafri; Mithuna Thottethodi; T. N. Vijaykumar (HPCA, 2010)

Timetraveler: exploiting acyclic races for optimizing memory race recording. - Gwendolyn Voskuilen; Faraz Ahmad; T. N. Vijaykumar (ISCA, 2010)

Adaptive Flow Control for Robust Performance and Energy. - Syed Ali Raza Jafri; Yu-Ju Hong; Mithuna Thottethodi; T. N. Vijaykumar (MICRO, 2010)

EffiCuts: optimizing packet classification for memory and throughput. - Balajee Vamanan; Gwendolyn Voskuilen; T. N. Vijaykumar (SIGCOMM, 2010)

TreeCAM: decoupling updates and lookups in packet classification. - Balajee Vamanan; T. N. Vijaykumar (CoNEXT, 2011)

Tarazu: optimizing MapReduce on heterogeneous clusters. - Faraz Ahmad; Srimat T. Chakradhar; Anand Raghunathan; T. N. Vijaykumar (ASPLOS, 2012)

Deadline-aware datacenter tcp (D2TCP). - Balajee Vamanan; Jahangir Hasan; T. N. Vijaykumar (SIGCOMM, 2012)

Top Picks from the 2011 Computer Architecture Conferences. - Paolo Faraboschi; T. N. Vijaykumar (IEEE Micro, 2012)

Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies. - Syed Ali Raza Jafri; Gwendolyn Voskuilen; T. N. Vijaykumar (ASPLOS, 2013)

MapReduce with communication overlap (MaRCO). - Faraz Ahmad; Seyong Lee; Mithuna Thottethodi; T. N. Vijaykumar (J. Parallel Distributed Comput., 2013)

High-performance fractal coherence. - Gwendolyn Voskuilen; T. N. Vijaykumar (ASPLOS, 2014)

Fractal++: Closing the performance gap between fractal and conventional coherence. - Gwendolyn Voskuilen; T. N. Vijaykumar (ISCA, 2014)

ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters. - Faraz Ahmad; Srimat T. Chakradhar; Anand Raghunathan; T. N. Vijaykumar (USENIX ATC, 2014)

FaultHound: value-locality-based soft-fault tolerance. - Nitin 002; Irith Pomeranz; T. N. Vijaykumar (ISCA, 2015)

TimeTrader: exploiting latency tail to save datacenter energy for online search. - Balajee Vamanan; Hamza Bin Sohail; Jahangir Hasan; T. N. Vijaykumar (MICRO, 2015)

MigrantStore: Leveraging Virtual Memory in DRAM-PCM Memory Architecture. - Hamza Bin Sohail; Balajee Vamanan; T. N. Vijaykumar (CoRR, 2015)

TimeTrader: Exploiting Latency Tail to Save Datacenter Energy for On-line Data-Intensive Applications. - Balajee Vamanan; Hamza Bin Sohail; Jahangir Hasan; T. N. Vijaykumar (CoRR, 2015)

Hydra: Leveraging functional slicing for efficient distributed SDN controllers. - Yiyang Chang; Ashkan Rezaei; Balajee Vamanan; Jahangir Hasan; Sanjay G. Rao; T. N. Vijaykumar (COMSNETS, 2017)

Exploring Functional Slicing in the Design of Distributed SDN Controllers. - Yiyang Chang; Ashkan Rezaei; Balajee Vamanan; Jahangir Hasan; Sanjay G. Rao; T. N. Vijaykumar (COMSNETS (Revised Selected Papers and Invited Papers), 2017)

Efficient Collaborative Approximation in MapReduce without Missing Rare Keys. - Nitin 002; Mithuna Thottethodi; T. N. Vijaykumar; Milind Kulkarni 001 (ICCAC, 2017)

NutShell: Scalable Whittled Proxy Execution for Low-Latency Web over Cellular Networks. - Ashiwan Sivakumar; Chuan Jiang; Yun Seong Nam; Shankaranarayanan Puzhavakath Narayanan; Vijay Gopalakrishnan; Sanjay G. Rao; Subhabrata Sen; Mithuna Thottethodi; T. N. Vijaykumar (MobiCom, 2017)

Millipede: Die-Stacked Memory Optimizations for Big Data Machine Learning Analytics. - Nitin 002; Mithuna Thottethodi; T. N. Vijaykumar (IPDPS, 2018)

Fast Congestion Control in RDMA-based Datacenter Networks. - Jaichen Xue; Muhammad Usama Chaudhry; Balajee Vamanan; T. N. Vijaykumar; Mithuna Thottethodi (SIGCOMM Posters and Demos, 2018)

Dart: Divide and Specialize for Fast Response to Congestion in RDMA-based Datacenter Networks. - Jaichen Xue; Muhammad Usama Chaudhry; Balajee Vamanan; T. N. Vijaykumar; Mithuna Thottethodi (CoRR, 2018)

SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks. - Ashish Gondimalla; Noah Chesnut; Mithuna Thottethodi; T. N. Vijaykumar (MICRO, 2019)

Secure automatic bounds checking: prevention is simpler than cure. - Ejebagom John Ojogbo; Mithuna Thottethodi; T. N. Vijaykumar (CGO, 2020)

Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning. - Mingxuan He; Choungki Song; Ilkon Kim; Chunseok Jeong; Seho Kim; Il Park 001; Mithuna Thottethodi; T. N. Vijaykumar (MICRO, 2020)

Booster: An Accelerator for Gradient Boosting Decision Trees. - Mingxuan He; T. N. Vijaykumar; Mithuna Thottethodi (CoRR, 2020)

Network Interface Architecture for Remote Indirect Memory Access (RIMA) in Datacenters. - Jiachen Xue; T. N. Vijaykumar; Mithuna Thottethodi (ACM Trans. Archit. Code Optim., 2020)

Dart: Divide and Specialize for Fast Response to Congestion in RDMA-Based Datacenter Networks. - Jiachen Xue; Muhammad Usama Chaudhry; Balajee Vamanan; T. N. Vijaykumar; Mithuna Thottethodi (IEEE/ACM Trans. Netw., 2020)

FastZ: accelerating gapped whole genome alignment on GPUs. - Sree Charan Gundabolu; T. N. Vijaykumar; Mithuna Thottethodi (SC, 2021)

Barrier-Free Large-Scale Sparse Tensor Accelerator (BARISTA) For Convolutional Neural Networks. - Ashish Gondimalla; Sree Charan Gundabolu; T. N. Vijaykumar; Mithuna Thottethodi (CoRR, 2021)

Karma: Cost-Effective Geo-Replicated Cloud Storage with Dynamic Enforcement of Causal Consistency. - Tariq Mahmood 005; Shankaranarayanan Puzhavakath Narayanan; Sanjay G. Rao; T. N. Vijaykumar; Mithuna Thottethodi (IEEE Trans. Cloud Comput., 2021)

Booster: An Accelerator for Gradient Boosting Decision Trees Training and Inference. - Mingxuan He; Mithuna Thottethodi; T. N. Vijaykumar (IPDPS, 2022)

Eureka: Efficient Tensor Cores for One-sided Unstructured Sparsity in DNN Inference. - Ashish Gondimalla; Mithuna Thottethodi; T. N. Vijaykumar (MICRO, 2023)

SafeBet: Secure, Simple, and Fast Speculative Execution. - Conor Green; Cole Nelson; Mithuna Thottethodi; T. N. Vijaykumar (CoRR, 2023)

Occam: Optimal Data Reuse for Convolutional Neural Networks. - Ashish Gondimalla; Jianqiao Liu; Mithuna Thottethodi; T. N. Vijaykumar (ACM Trans. Archit. Code Optim., 2023)

QED: Scalable Verification of Hardware Memory Consistency. - Gokulan Ravi; Xiaokang Qiu; Mithuna Thottethodi; T. N. Vijaykumar (CoRR, 2024)

Efficient Sparse Processing-in-Memory Architecture (ESPIM) for Machine Learning Inference. - Mingxuan He; Mithuna Thottethodi; T. N. Vijaykumar (CoRR, 2024)