A dual-channel voice-band PCM codec using Sigma Delta modulation technique. - Vladimir Friedman; Douglas M. Brinthaupt; De-Ping Chen; Timothy W. Deppa; John P. Elward Jr.; Evelyn M. Fields; Jeffrey W. Scott; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 1989)

A 10-b 20-Msample/s analog-to-digital converter. - Stephen H. Lewis; H. Scott Fetterman; George F. Gross; Ravi Ramachandran; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 1992)

A Non-uniform Sampling Technique for A/D Conversion. - N. Sayiner; Henrik V. Sorensen; T. R. Viswanathan 001 (ISCAS, 1993)

Efficient 6-bit A/D converter using a 1-bit folding front end. - K. Nagaraj; F. Chen; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 1999)

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. - Krishnaswamy Nagaraj; David A. Martin; Mark A. Wolfe; Ranjan Chattopadhyay; Shanthi Pavan; Jason Cancio; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2000)

A CMOS bandgap reference without resistors. - Arne E. Buck; Charles L. McDonald; Stephen H. Lewis; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2002)

A Unity-Gain Buffer with Reduced Offset and Gain Error. - Guangmao Xing; Stephen H. Lewis; T. R. Viswanathan 001 (CICC, 2006)

A 1.4 V Supply CMOS Fractional Bandgap Reference. - Raymond T. Perry; Stephen H. Lewis; A. Paul Brokaw; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2007)

CMOS Latch Using Quad for High-Speed Comparators. - Venkatesh Acharya; T. Lakshmi Viswanathan; Thayamkulangara R. Viswanathan (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A highly linear CMOS current-controlled oscillator using a novel frequency detector. - Su Cui; T. Lakshmi Viswanathan; Thayamkulangara R. Viswanathan; Bhaskar Banerjee (ISCAS, 2008)

Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems. - Ajay Taparia; Thayamkulangara R. Viswanathan (ISCAS, 2008)

A Low-Supply-Voltage CMOS Sub-Bandgap Reference. - Adriana Becker-Gomez; T. Lakshmi Viswanathan; Thayamkulangara R. Viswanathan (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Self-Biased Unity-Gain Buffers With Low Gain Error. - Guangmao Xing; Stephen H. Lewis; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator. - Joseph Hamilton; Shouli Yan; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Two-Stage ADC Architecture With VCO-Based Second Stage. - Amit Kumar Gupta; Krishnaswamy Nagaraj; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems. - Ajay Taparia; Bhaskar Banerjee; Thayamkulangara R. Viswanathan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs. - Ajay Taparia; Bhaskar Banerjee; Thayamkulangara R. Viswanathan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC. - Joseph Hamilton; Shouli Yan; T. R. Viswanathan 001 (CICC, 2012)

Clock-gated harmonic rejection mixers. - Aslam A. Rafi; T. R. Viswanathan 001 (CICC, 2012)

A digital bandgap reference. - Adriana Becker-Gomez; Antonio F. Mondragón-Torres; Venkatesh Acharya; Bhaskar Banerjee; Thayamkulangara R. Viswanathan (MWSCAS, 2013)

Operational current to frequency converter. - Rohit Yadav; K. R. Raghunandan; Ananth Dodabalapur; T. Lakshmi Viswanathan; T. R. Viswanathan 001 (MWSCAS, 2013)

Harmonic Rejection Mixing Techniques Using Clock-Gating. - Aslam A. Rafi; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2013)

Linear current-controlled oscillator for analog to digital conversion. - K. R. Raghunandan; T. Lakshmi Viswanathan; Thayamkulangara R. Viswanathan (CICC, 2014)

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. - Arindam Sanyal; Kareem Ragab; Long Chen 004; T. R. Viswanathan 001; Shouli Yan; Nan Sun 001 (CICC, 2014)

A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. - Amit Kumar Gupta; Krishnaswamy Nagaraj; T. R. Viswanathan 001 (MWSCAS, 2014)

Analog signal processing in deep submicron CMOS technologies using inverters. - K. R. Raghunandan; Nan Sun 003; T. R. Viswanathan 001 (MWSCAS, 2014)

Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications. - Sudhanva Vasishta; K. R. Raghunandan; Ananth Dodabalapur; T. R. Viswanathan 001 (MWSCAS, 2020)

A Novel Low-Power Single-step Subranging Open-loop Sigma-Delta ADC. - Sudhanva Vasishta; K. R. Raghunandan; Ananth Dodabalapur; Thayamkulangara R. Viswanathan (MWSCAS, 2021)

A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC. - Sudhanva Vasishta; K. R. Raghunandan; Ananth Dodabalapur; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)