Modified Metaheuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters. - T. S. Bindiya; Elizabeth Elias (Circuits Syst. Signal Process., 2014)

Metaheuristic algorithms for the design of multiplier-less non-uniform filter banks based on frequency response masking. - T. S. Bindiya; Elizabeth Elias (Soft Comput., 2014)

Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks. - T. S. Bindiya; Elizabeth Elias (Inf. Sci., 2016)

Reconfigurable Non-Maximally Decimated Filter Bank based wideband channelizer for VLBI. - Sudhi Sudharman; T. S. Bindiya (CCECE, 2017)

Design and implementation of reconfigurable filter bank structure for low complexity hearing aids using 2-level sound wave decomposition. - Amir A.; T. S. Bindiya; Elizabeth Elias (Biomed. Signal Process. Control., 2018)

A New Multiplier-free Transformation for the Design of Hardware Efficient Circularly Symmetric Wideband 2D Filters. - K. R. Sreelekha; T. S. Bindiya (TENCON, 2019)

Design and Implementation of Maximally Decimated Polyphase Filter Bank for Power and Delay Efficient Digital Hearing Aids. - Sudhi Sudharman; T. S. Bindiya (TENCON, 2019)

Low-complexity implementation of efficient reconfigurable structure for cost-effective hearing aids using fractional interpolation. - Amir A.; T. S. Bindiya; Elizabeth Elias (Comput. Electr. Eng., 2019)

Design of a Power-Efficient Low-Complexity Reconfigurable Non-maximally Decimated Filter Bank for High-Resolution Wideband Channels. - Sudhi Sudharman; Athul D. Rajan; T. S. Bindiya (Circuits Syst. Signal Process., 2019)

Design of Power Efficient Variable Bandwidth Non-Maximally Decimated FRM Filters for Wideband Channelizer. - Sudhi Sudharman; T. S. Bindiya (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Multiplier-free Realization of High Throughout Transpose Form FIR Filter. - Sudhi Sudharman; T. S. Bindiya (CSNDSP, 2020)

Design of Low-Complex Linear-Phase Non-uniform Filter Bank to Realize Wavelet Approximation of Bark Frequency Partitioning for Real-Time Applications. - Hareesh V.; T. S. Bindiya (Circuits Syst. Signal Process., 2020)

Analysis of Different Rational Decimated Filter Banks Derived From the Same Set of Prototype Filters. - Hareesh V.; T. S. Bindiya (IEEE Trans. Signal Process., 2020)

High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network. - Tresa Joseph; T. S. Bindiya (VDAT, 2021)

Design of Reconfigurable FRM Channelizer using Resource Shared Non-maximally Decimated Masking Filters. - Sudhi Sudharman; T. S. Bindiya (J. Signal Process. Syst., 2021)

Design of Hardware Efficient Reconfigurable Merged Partial Cosine Modulated Non-uniform Filter Bank Channelizer and its Power Efficient Implementation Using a Novel Approximation Algorithm. - Hareesh V.; T. S. Bindiya (Circuits Syst. Signal Process., 2022)

Design of variable elliptical filters with direct tunability in 2D domain. - K. R. Sreelekha; T. S. Bindiya (Multidimens. Syst. Signal Process., 2022)

Development of a 2D Filter Architecture to Obtain Circular Bandwidths Varied by Arbitrary Rational Values Without Restructuring. - K. R. Sreelekha; T. S. Bindiya (Circuits Syst. Signal Process., 2023)

Design of cost effective variable bandwidth 2D low-pass, high-pass and band-pass filters with improved circularity. - K. R. Sreelekha; T. S. Bindiya (Digit. Signal Process., 2023)

Development of variable 2D FIR filter structures using farrow approximation and row-wise polyphase decomposition. - K. R. Sreelekha; T. S. Bindiya (Digit. Signal Process., 2023)

Performance-Driven LSTM Accelerator Hardware Using Split-Matrix-Based MVM. - Tresa Joseph; T. S. Bindiya (Circuits Syst. Signal Process., 2023)

Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders. - Tresa Joseph; T. S. Bindiya (Circuits Syst. Signal Process., 2023)

Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions. - Tresa Joseph; T. S. Bindiya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI. - Mrinmay Sasmal; Tresa Joseph; T. S. Bindiya (IEEE Comput. Archit. Lett., 2024)

An Improved Rational Approximation of Bark Scale Using Low Complexity and Low Delay Filter Banks. - Hareesh V.; T. S. Bindiya (Circuits Syst. Signal Process., 2024)