Pre-silicon prototyping of a unified hardware architecture for cryptographic manipulation detection codes. - T. S. Ganesh; T. S. B. Sudarshan; Naveen Kumar Srinivasan; Karthick Jayapal (FPT, 2004)

Caching and replacement of streaming objects based on a popularity function. - T. S. B. Sudarshan; T. S. Ganesh; G. Raghurama (Communications and Computer Networks, 2005)

ASIC Implementation of a Unified Hardware Architecture for Non-Key Based Cryptographic Hash Primitives. - T. S. Ganesh; T. S. B. Sudarshan (ITCC (1), 2005)

SEU Mitigation Techniques for Microprocessor Control Logic. - T. S. Ganesh; Viswanathan Subramanian; Arun K. Somani (EDCC, 2006)

Hashchip: A shared-resource multi-hash function processor architecture on FPGA. - T. S. Ganesh; Michael T. Frederick; T. S. B. Sudarshan; Arun K. Somani (Integr., 2007)

Greedy Dynamic Crossover Management in Hardware Accelerated Genetic Algorithm Implementations Using FPGA. - Shubhalaxmi Kher; T. S. Ganesh; Prem Ramesh; Arun K. Somani (UKSim, 2009)