Design and FPGA implementation of digit-serial FIR filters. - Javier Valls; Marcos M. Peiró; Trinidad Sansaloni; Eduardo I. Boemo (ICECS, 1998)

A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. - Marcos Martínez-Peiró; Javier Valls; T. Sansaloni; A. Perez-Pascual; Eduardo I. Boemo (ICECS, 1999)

FPGA-based digit-serial complex number multiplier-accumulator. - Trinidad Sansaloni; Javier Valls; Keshab K. Parhi (ISCAS, 2000)

FPGA based on-line complex-number multipliers. - A. Perez-Pascual; T. Sansaloni; Javier Valls (ICECS, 2001)

Distributed arithmetic radix-2 butterflies for FPGA. - T. Sansaloni; A. Perez-Pascual; Javier Valls (ICECS, 2001)

FPGA-based radix-4 butterflies for HIPERLAN/2. - A. Perez-Pascual; T. Sansaloni; Javier Valls (ISCAS (3), 2002)

DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. - José Marín-Roig; Vicente Torres-Carot; Ma José Canet; Asuncion Perez-Pascual; Trinidad Sansaloni; Francisco Cardells-Tormo; Fabian Angarita; Felip Vicedo; Vicenc Almenar-Terre; Javier Valls-Coquillat (FPL, 2003)

Digit-Serial Complex-Number Multipliers on FPGAs. - T. Sansaloni; Javier Valls; Keshab K. Parhi (J. VLSI Signal Process., 2003)

Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. - Fabian Angarita; A. Perez-Pascual; T. Sansaloni; Javier Valls (FPL, 2005)

Design of high performance timing recovery loops for communication applications. - Vicente Torres-Carot; A. Perez-Pascual; T. Sansaloni; Javier Valls (SiPS, 2006)

The use of CORDIC in software defined radios: a tutorial. - Javier Valls; Trinidad Sansaloni; Asuncion Perez-Pascual; Vicente Torres 001; Vicenç Almenar (IEEE Commun. Mag., 2006)

Design of an efficient digital down-converter for a SDR-based DVB-S receiver. - A. Perez-Pascual; T. Sansaloni; Vicente Torres 001; Vicenç Almenar; Javier Valls (ECCTD, 2007)

Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN. - Fabian Angarita Preciado; María José Canet; Trinidad Sansaloni Balaguer; Vicenc Almenar-Terre; Javier Valls-Coquillat (ICECS, 2007)

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. - Trinidad Sansaloni; Asuncion Perez-Pascual; Vicente Torres-Carot; Vicenç Almenar; José F. Toledo; Javier Valls (IEEE Trans. Educ., 2007)

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. - T. Sansaloni; A. Perez-Pascual; Vicente Torres-Carot; Javier Valls (J. VLSI Signal Process., 2007)

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. - Fabian Angarita; Ma José Canet; T. Sansaloni; A. Perez-Pascual; Javier Valls (J. Signal Process. Syst., 2008)

Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. - Fabian Angarita; Ma José Canet; T. Sansaloni; Javier Valls; Vicenc Almenar-Terre (J. Signal Process. Syst., 2008)

Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. - Fabian Angarita; Ma José Canet; Trinidad Sansaloni; Vicenç Almenar; Javier Valls (J. Circuits Syst. Comput., 2009)

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. - A. Perez-Pascual; T. Sansaloni; Vicente Torres-Carot; Vicenc Almenar-Terre; Javier Valls (J. Signal Process. Syst., 2009)

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. - Vicente Torres-Carot; A. Perez-Pascual; T. Sansaloni; Javier Valls (J. Signal Process. Syst., 2009)

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. - Vicente Torres-Carot; Asuncion Perez-Pascual; Trinidad Sansaloni; Javier Valls (ICECS, 2012)

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. - Fabian Angarita; Trinidad Sansaloni; María José Canet; Javier Valls (J. Signal Process. Syst., 2012)

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. - Fabian Angarita; Trinidad Sansaloni; Asuncion Perez-Pascual; Javier Valls (J. Signal Process. Syst., 2012)