A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. - Nicky Chau-Chun Lu; Gary B. Bronner; Koji Kitamura; Roy E. Scheuerlein; Walter H. Henkels; Sang H. Dhong; Yasunao Katayama; Toshiaki Kirihata; Hideto Niijima; Robert L. Franch; Wei Wang; Motoo Nishiwaki; et al. (IEEE J. Solid State Circuits, 1989)

Designing a Testable System on a Chip. - Stephen V. Kosonocky; Arthur A. Bright; Kevin W. Warren; Ruud A. Haring; Steve Klepner; Sameh W. Asaad; S. Basavaiah; Bob Havreluk; David F. Heidel; Michael Immediato; Keith A. Jenkins; Rajiv V. Joshi; et al. (VTS, 1998)