Core Interconnect Testing Hazards. - Petra Nordholz; Hartmut Grabinski; Dieter Treytnar; Jan Otterstedt; Dirk Niggemeyer; Uwe Arz; T. W. Williams (DATE, 1998)

Tecolote: An Object-Oriented Framework for Physics Development. - J. C. Marshall; L. A. Ankeny; S. P. Clancy; J. H. Hall; J. H. Heiken; K. S. Holian; Stephen R. Lee; G. R. McNamara; J. W. Painter; M. E. Zander; Julian Cummings; Scott Haney; et al. (ECOOP Workshops, 1998)

Detection of CMOS address decoder open faults with March and pseudo random memory tests. - Jan Otterstedt; Dirk Niggemeyer; T. W. Williams (ITC, 1998)

Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores. - Petra Nordholz; Dieter Treytnar; Jan Otterstedt; Hartmut Grabinski; Dirk Niggemeyer; T. W. Williams (VTS, 1998)

A D&T Roundtable: Testing Mixed Logic and DRAM Chips. - Meh-Ron Amerian; William D. Atwell Jr.; Ian Burgess; Gary D. Fleeman; David Y. Lepejian; T. W. Williams; Farzad Zarrinfar; Yervant Zorian (IEEE Des. Test Comput., 1998)

Invited Talk 2: EDA to the Rescue of the Silicon Roadmap. - T. W. Williams (ATS, 2007)