COM (Cost Oriented Memory) Testing. - T. Yamada; Akihiro Fujiwara; Michiko Inoue (ITC, 1992)

Extending the Application of a Neural Network for Failure Analysis of Electronic Circuit Boards. - H. Tabuchi; T. Yamada; M. Usami; M. Nagao; K. Moki; T. Ochiai; M. Kawai (IIA/SOCO, 1999)

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. - Vineet Agrawal; N. Kepler; David Kidd; Gokul Krishnan; Samuel Leshner; T. Bakishev; D. Zhao; P. Ranade; R. Roy; M. Wojko; Lawrence T. Clark; Robert Rogenmoser; et al. (CICC, 2013)

Silicon Photonics Coherent Optical Subassembly with EO and OE Bandwidths of over 50 GHz. - Shogo Yamanaka; Y. Ikuma; Toshihiro Itoh; Yuriko Kawamura; Kiyofumi Kikuchi; Y. Kurata; Makoto Jizodo; Teruo Jyo; S. Soma; Masayuki Takahashi; Ken Tsuzuki; Munehiko Nagatani; et al. (OFC, 2020)