High-Level Decision Diagram based Fault Models for Targeting FSMs. - Jaan Raik; Raimund Ubar; Taavi Viilukas (DSD, 2006)

Mixed hierarchical-functional fault models for targeting sequential cores. - Jaan Raik; Raimund Ubar; Taavi Viilukas; Maksim Jenihhin (J. Syst. Archit., 2008)

Constraint-based test pattern generation at the Register-Transfer Level. - Taavi Viilukas; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Anna Krivenko (DDECS, 2010)

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. - Jaan Raik; Anna Rannaste; Maksim Jenihhin; Taavi Viilukas; Raimund Ubar; Hideo Fujiwara (ETS, 2011)

Automated test bench generation for high-level synthesis flow ABELITE. - Taavi Viilukas; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Samary Baranov (EWDTS, 2011)

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. - Taavi Viilukas; Anton Karputkin; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Hideo Fujiwara (J. Electron. Test., 2012)