Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops. - P. Mohanraj; David D. Falconer; Tad A. Kwasniewski (IEEE J. Sel. Areas Commun., 1991)

Delta-sigma modulation in fractional-N frequency synthesis. - Tom A. D. Riley; Miles A. Copeland; Tad A. Kwasniewski (IEEE J. Solid State Circuits, 1993)

A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems. - D. P. Noel; Tad A. Kwasniewski; Samy A. Mahmoud; Wilf P. LeBlanc (VTC, 1994)

A chip set for pipeline and parallel pipeline FFT architectures. - Valek Szwarc; Luc Desormeaux; Wilson Wong; Clifford P. S. Yeung; Chong H. Chan; Tad A. Kwasniewski (J. VLSI Signal Process., 1994)

CMOS high-speed dual-modulus frequency divider for RF frequency synthesis. - Navid Foroudi; Tadeusz Kwasniewski (IEEE J. Solid State Circuits, 1995)

Is High Frequency Analog DFT Possible? - Bozena Kaminska; Tad A. Kwasniewski; Linda S. Milor; G. Roberts; P. Flahive; Jérôme Wojcik (VTS, 1996)

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications. - Manop Thamsirianunt; Tadeusz Kwasniewski (IEEE J. Solid State Circuits, 1997)

A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications. - Lizhong Sun; Tad A. Kwasniewski (CICC, 1999)

A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops. - Lizhong Sun; Tad A. Kwasniewski; Kris Iniewski (ISCAS (2), 1999)

Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. - Lizhong Sun; Thierry Lepley; Franck Nozahic; Amaud Bellissant; Tad A. Kwasniewski; Bany Heim (ISCAS (2), 1999)

A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. - Lizhong Sun; Tadeusz Kwasniewski (IEEE J. Solid State Circuits, 2001)

A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (CICC, 2003)

2.4 GHz RF down-conversion mixers in standard CMOS technology. - Arif A. Siddiqi; Tad A. Kwasniewski (ISCAS (4), 2004)

Design and comparison of CMOS Current Mode Logic latches. - Muhammad Usama; Tad A. Kwasniewski (ISCAS (4), 2004)

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. - Miao Li; Tad A. Kwasniewski; Shoujun Wang; Yuming Tao (ASP-DAC, 2005)

Behavioral test benches for digital clock and data recovery circuits using Verilog-A. - S. I. Ahmed; Kent Orthner; Tadeusz Kwasniewski (CICC, 2005)

A signal integrity-based link performance simulation platform. - Yuming Tao; William Bereza; Rakesh H. Patel; Sergey Y. Shumarayev; Tad A. Kwasniewski (CICC, 2005)

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. - Shoujun Wang; Haitao Mei 002; Mashkoor Baig; William Bereza; Tadeusz Kwasniewski; Rakesh H. Patel (CICC, 2005)

A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (Circuits, Signals, and Systems, 2005)

An all-digital data recovery circuit optimization using Matlab/Simulink. - S. I. Ahmed; Tad A. Kwasniewski (ISCAS (5), 2005)

Decision feedback equalization for high-speed backplane data communications. - Jing Chen; Miao Li; Tad A. Kwasniewski (ISCAS (2), 2005)

A 0.18µm CMOS transceiver design for high-speed backplane data communications. - Miao Li; Wenjie Huang; Tad A. Kwasniewski; Shoujun Wang (ISCAS (2), 2005)

A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane. - Charles E. Berndt; Tad A. Kwasniewski (IWSOC, 2005)

Turbo Codes - Digital IC Design. - Moeed Israr; Tad A. Kwasniewski (IWSOC, 2005)

Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. - Miao Li; Peter Noel; Tad A. Kwasniewski; Shoujun Wang (IWSOC, 2005)

PLL-Based Fractional-N Frequency Synthesizers. - Farhad Zarkeshvari; Peter Noel; Tad A. Kwasniewski (IWSOC, 2005)

A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications. - Miao Li; Tad A. Kwasniewski; Shoujun Wang (APCCAS, 2006)

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (CCECE, 2006)

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (CICC, 2006)

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. - William Bereza; Yuming Tao; Shoujun Wang; Tad A. Kwasniewski; Rakesh H. Patel (DAC, 2006)

A 0.18µm CMOS clock and data recovery circuit with extended operation range. - Miao Li; Wenjie Huang; Tad A. Kwasniewski; Shoujun Wang (ISCAS, 2006)

An eye detection technique for clock and data recovery applications. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (ISCAS, 2006)

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (SoCC, 2006)

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (CICC, 2007)

Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation. - Ramin Shariat-Yazdi; Tadeusz Kwasniewski (ICECS, 2007)

A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology. - Muhammad Usama; Tad A. Kwasniewski (ISCAS, 2007)

Design Considerations for a Direct RF Sampling Mixer. - Dianyong Chen; Wei Wang; Tadeusz Kwasniewski (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. - Tingjun Wen; Tadeusz Kwasniewski (BMAS, 2008)

A 42-Gb/s Decision Circuit in 0.13µm CMOS. - Bangli Liang; Tad A. Kwasniewski; Dianyong Chen (CNSR, 2008)

A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. - Miao Li; Tad A. Kwasniewski; Shoujun Wang (ISCAS, 2008)

Low complexity sphere decoding algorithms. - Ramin Shariat-Yazdi; Tad A. Kwasniewski (ISWCS, 2008)

A multi-mode sphere detector architecture for WLAN applications. - Ramin Shariat-Yazdi; Tad A. Kwasniewski (SoCC, 2008)

A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously. - Dianyong Chen; Bo Wang; Bangli Liang; Tad A. Kwasniewski (CCECE, 2009)

A full-rate truly monolithic CMOS CDR for low-cost applications. - Bangli Liang; Zhigong Wang; Dianyong Chen; Bo Wang; Guohui Situ; Tad A. Kwasniewski (CCECE, 2009)

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. - Bo Wang; Dianyong Chen; Bangli Liang; Jinguang Jiang; Tad A. Kwasniewski (CCECE, 2009)

A monolithic high modulation efficiency CMOS laser diode / modulator driver. - Bangli Liang; Dianyong Chen; Bo Wang; Guohui Situ; Tad A. Kwasniewski; Zhigong Wang (ICT, 2009)

A Simulator for High-Speed Backplane Transceivers. - Dianyong Chen; Bo Wang; Bangli Liang; Tadeusz Kwasniewski (UKSim, 2009)

Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel. - Bo Wang; Dianyong Chen; Bangli Liang; Jinguang Jiang; Tadeusz Kwasniewski (UKSim, 2009)

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. - Huong Ho; Valek Szwarc; Tad A. Kwasniewski (Int. J. Reconfigurable Comput., 2009)

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission. - Lei Zhang; Tadeusz Kwasniewski (Microelectron. J., 2009)

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Optimized LNA for analog RF front-end circuit in brain-machine interface. - Haizheng Guo; Bo Wang; Bangli Liang; Tad A. Kwasniewski; Robert Sobot (WCNIS, 2010)

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. - Huong Ho; Valek Szwarc; Tad A. Kwasniewski (J. Signal Process. Syst., 2010)

A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system. - Harry Tai; Peter Noel; Tad A. Kwasniewski (SoCC, 2011)

A DLL-based fractional-N frequency synthesizer with a programmable injection clock. - Haizheng Guo; Tad A. Kwasniewski (CCECE, 2012)

Bang-Bang CDR's acquisition, locking, and jitter tolerance. - Chao He; Tadeusz Kwasniewski (CCECE, 2012)

A novel fractional-N PLL architecture with hybrid of DCO and VCO. - Chao He; Tadeusz Kwasniewski (CCECE, 2012)

Spur analysis and reduction of edge combining DLL-based frequency multiplier. - Haizheng Guo; Xinjie Wang; Tadeusz Kwasniewski (CCECE, 2013)

A DLL-based period synthesis. - Haizheng Guo; Tadeusz Kwasniewski (CCECE, 2015)

A DLL fractional M/N frequency synthesizer. - Haizheng Guo; Tadeusz Kwasniewski (CCECE, 2015)

Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example. - Zhe Jiang; Haizheng Guo; Tadeusz Kwasniewski (CCECE, 2015)

A reduced reference spur multiplying delay-locked loop. - Xinjie Wang; Tadeusz Kwasniewski (Int. J. Circuit Theory Appl., 2016)

On-die power grid broadband model determination using a priori narrowband measurements. - Leonard MacEachem; Xin-Jie Wang; Tad A. Kwasniewski (MWSCAS, 2017)