A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI. - Masakazu Yamashina; Junichi Goto; Fuyuki Okamoto; Koichi Ando; Hachiro Yamada; Tadahiko Horiuchi; Kimiko Nakamura; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1989)

A 300-MHz 16-b BiCMOS video signal processor. - Toshiaki Inoue; Junichi Goto; Masakazu Yamashina; Kazumasa Suzuki; Masahiro Nomura; Youichi Koseki; Tohru Kimura; Takao Atsumo; Masato Motomura; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; et al. (IEEE J. Solid State Circuits, 1993)

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. - Masahiro Nomura; Masakazu Yamashina; Junichi Goto; Toshiaki Inoue; Kazumasa Suzuki; Masato Motomura; Youichi Koseki; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; Kouichi Kumagai; Tadayoshi Enomoto; et al. (IEEE J. Solid State Circuits, 1994)

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. - Tomofumi lima; Masayuki Mizuno; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1996)

A 0.25-μm CMOS 0.9-V 100-MHz DSP core. - Masanori Izumikawa; Hiroyuki Igura; Hitoshi Wakabayashi; Ken Nakajima; Tohru Mogami; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1997)

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. - Kenji Noda; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hiroyuki Kawamoto; Nobuyuki Ikezawa; Koichi Takeda 001; Yoshiharu Aimoto; Naoto Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Tadahiko Horiuchi (CICC, 2000)

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. - Koichi Takeda 001; Yoshiharu Aimoto; Noritsugu Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Kenji Noda; Koujirou Matsui; Shinya Itoh; Sadaaki Masuoka; Tadahiko Horiuchi; Atsushi Nakagawa; Kenju Shimogawa; et al. (IEEE J. Solid State Circuits, 2000)

A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. - Koichiro Minami; Muneo Fukaishi; Masayuki Mizuno; Hideaki Onishi; Kenji Noda; Kiyotaka Imai; Tadahiko Horiuchi; Hiroshi Yamaguchi; Takanori Sato; Kazuyuki Nakamura; Masakazu Yaniashina (CICC, 2001)

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. - Kenji Noda; Koichi Takeda 001; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hideaki Kawamoto; Nobuyuki Ikezawa; Yoshiharu Aimoto; Noritsugu Nakamura; Takahiro Iwasaki; Hideo Toyoshima; Tadahiko Horiuchi (IEEE J. Solid State Circuits, 2001)

Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance. - Shinya Ito; Hiroaki Namba; Tsuyoshi Hirata; Koichi Ando; Shin Koyama; Nobuyuki Ikezawa; Tatsuya Suzuki; Takehiro Saitoh; Tadahiko Horiuchi (Microelectron. Reliab., 2002)