Automated bias control (ABC) circuit for high-performance VLSIs. - Tadahiro Kuroda; Toshiyuki Fukunaga; Kenji Matsuo; Kazuhiko Kasai; Ayako Hirata; Shinji Fujii; Masahiro Kimura; Hiroaki Suzuki (IEEE J. Solid State Circuits, 1992)

Analysis and optimization of BiCMOS gate circuits. - Tadahiro Kuroda; Yoshinori Sakata; Kenji Matsuo (IEEE J. Solid State Circuits, 1994)

Substrate noise influence on circuit performance in variable threshold-voltage scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Toshiaki Mori; Kenji Matsuo; Masakazu Kakumu; Takayasu Sakurai (ISLPED, 1996)

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakurnu; et al. (IEEE J. Solid State Circuits, 1996)

Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. - Tadahiro Kuroda; Tetsuya Fujita; Makato Noda; Yasushi Itabashi; Satohiko Kabumoto; T. S. Wong; Dave Beeson; Dave Gray (IEEE J. Solid State Circuits, 1996)

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. - Tadahiro Kuroda; Takayasu Sakurai (J. VLSI Signal Process., 1996)

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. - Mototsugu Hamada; Masafumi Takahashi; Hideho Arakida; Akihiko Chiba; Toshihiro Terazawa; Takashi Ishikawa; Masahiro Kanazawa; Mutsunori Igarashi; Kimiyoshi Usami; Tadahiro Kuroda (CICC, 1998)

Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. - Kimiyoshi Usami; Mutsunori Igarashi; Takashi Ishikawa; Masahiro Kanazawa; Masafumi Takahashi; Mototsugu Hamada; Hideho Arakida; Toshihiro Terazawa; Tadahiro Kuroda (DAC, 1998)

Variable supply-voltage scheme for low-power high-speed CMOS digital design. - Tadahiro Kuroda; Kojiro Suzuki; Shinji Mita; Tetsuya Fujita; Fumiyuki Yamane; Fumihiko Sano; Akihiko Chiba; Yoshinori Watanabe; Koji Matsuda; Takeo Maeda; Takayasu Sakurai; Tohru Furuyama (IEEE J. Solid State Circuits, 1998)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. - Masafumi Takahashi; Mototsugu Hamada; Tsuyoshi Nishikawa; Hideho Arakida; Tetsuya Fujita; Fumitoshi Hatori; Shinji Mita; Kojiro Suzuki; Akihiko Chiba; Toshihiro Terazawa; Fumihiko Sano; Yoshinori Watanabe; et al. (IEEE J. Solid State Circuits, 1998)

Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec. - Fuyuki Ichiba; Kojiro Suzuki; Shinji Mita; Tadahiro Kuroda; Tohru Furuyama (ISLPED, 1999)

Low-power CMOS digital design with dual embedded adaptive power supplies. - Tadahiro Kuroda; Mototsugu Hamada (IEEE J. Solid State Circuits, 2000)

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. - Masafumi Takahashi; Tsuyoshi Nishikawa; Mototsugu Hamada; Toshinari Takayanagi; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Ohashi; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; et al. (IEEE J. Solid State Circuits, 2000)

Utilizing surplus timing for power reduction. - Mototsugu Hamada; Yukio Ootaguro; Tadahiro Kuroda (CICC, 2001)

A bitline leakage compensation scheme for low-voltage SRAMs. - Ken-ichi Agawa; Hiroyuki Hara; Toshinari Takayanagi; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2001)

Optimization and control of VDD and VTH for low-power, high-speed CMOS design. - Tadahiro Kuroda (ICCAD, 2002)

Low-Power, High-Speed CMOS VLSI Design. - Tadahiro Kuroda (ICCD, 2002)

Practical methodology of post-layout gate sizing for 15% more power saving. - Noriyuki Miura; Naoki Kato; Tadahiro Kuroda (ASP-DAC, 2004)

Cross talk countermeasures in inductive inter-chip wireless superconnect. - Noriyuki Miura; Daisuke Mizoguchi; Takayasu Sakurai; Tadahiro Kuroda (CICC, 2004)

A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template. - Yuichi Hori; Kenji Shimizu; Yutaka Nakamura; Tadahiro Kuroda (ICPR (1), 2004)

Transceiver circuits for pulse-based ultra-wideband. - Takahide Terada; Shingo Yoshizumi; Yukitoshi Sanada; Tadahiro Kuroda (ISCAS (4), 2004)

Introduction to the Special Issue. - Bruce Gieseke; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. - Noriyuki Miura; Daisuke Mizoguchi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. - Yusuke Okaniwa; Hirotaka Tamura; Masaya Kibune; Daisuke Yamazaki; Tsz-Shing Cheung; Junji Ogawa; Nestoras Tzartzanis; William W. Walker; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. - Yasumoto Tomita; Masaya Kibune; Junji Ogawa; William W. Walker; Hirotaka Tamura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. - Kohei Onizuka; Hiroshi Kawaguchi 001; Makoto Takamiya; Tadahiro Kuroda; Takayasu Sakurai (CICC, 2006)

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2006)

A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. - Yasumoto Tomita; Hirotaka Tamura; Masaya Kibune; Junji Ogawa; Kohtaroh Gotoh; Tadahiro Kuroda (ISSCC, 2006)

Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. - Amit Kumar 022; Noriyuki Miura; Muhammad Muqsith; Tadahiro Kuroda (VLSI Design, 2006)

System LSI: Challenges and Opportunities. - Tadahiro Kuroda (IEICE Trans. Electron., 2006)

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. - Daisuke Mizoguchi; Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2006)

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2006)

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding. - Takahide Terada; Shingo Yoshizumi; Muhammad Muqsith; Yukitoshi Sanada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2006)

A 1Tb/s 3W Inductive-Coupling Transceiver Chip. - Noriyuki Miura; Tadahiro Kuroda (ASP-DAC, 2007)

Wideband Inductive-coupling Interface for High-performance Portable System. - Hiroki Ishikuro; Noriyuki Miura; Tadahiro Kuroda (CICC, 2007)

A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. - Vishal V. Kulkarni; Muhammad Muqsith; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2007)

An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. - Hiroki Ishikuro; Toshihiko Sugahara; Tadahiro Kuroda (ISSCC, 2007)

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2007)

A 40-to-44Gb/s 3? Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (ISSCC, 2007)

Special Section on Low-Power, High-Speed LSIs and Related Technologies. - Tadahiro Kuroda (IEICE Trans. Electron., 2007)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. - Kiichi Niitsu; Noriyuki Miura; Mari Inoue; Yoshihiro Nakagawa; Masamoto Tago; Masayuki Mizuno; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

18-GHz Clock Distribution Using a Coupled VCO Array. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

A 0.79-mm2 29-mW Real-Time Face Detection Core. - Yuichi Hori; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. - Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (IEEE J. Solid State Circuits, 2007)

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. - Yasumoto Tomita; Hirotaka Tamura; Masaya Kibune; Junji Ogawa; Kohtaroh Gotoh; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

Speaker Siglet Detection for Business Microscope. - Jun Nishimura; Nobuo Sato; Tadahiro Kuroda (ICMLA, 2008)

A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. - Lechang Liu; Makoto Takamiya; Tsuyoshi Sekitani; Yoshiaki Noguchi; Shintaro Nakano; Koichiro Zaitsu; Tadahiro Kuroda; Takao Someya; Takayasu Sakurai (ISSCC, 2008)

An 11Gb/s Inductive-Coupling Link with Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2008)

Eating habits monitoring using wireless wearable in-ear microphone. - Jun Nishimura; Tadahiro Kuroda (ISWPC, 2008)

Speech "Siglet" Detection for Business Microscope (concise contribution). - Jun Nishimura; Nobuo Sato; Tadahiro Kuroda (PerCom, 2008)

Constant Magnetic Field Scaling in Inductive-Coupling Data Link. - Daisuke Mizoguchi; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2008)

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Kiichi Niitsu; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. - Yoichi Yoshida; Noriyuki Miura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A wireless real-time on-chip bus trace system. - Shusuke Kawai; Takayuki Ikari; Yutaka Takikawa; Hiroki Ishikuro; Tadahiro Kuroda (ASP-DAC, 2009)

A 1 GHz CMOS comparator with dynamic offset control technique. - Xiaolei Zhu 002; Sanroku Tsukamoto; Tadahiro Kuroda (ASP-DAC, 2009)

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2009)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. - Shotaro Saito; Yoshinori Kohama; Yasufumi Sugimori; Yohei Hasegawa; Hiroki Matsutani; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Tadahiro Kuroda; Hideharu Amano (FPL, 2009)

Face detection through compact classifier using Adaptive Look-Up-Table. - Yuya Hanai; Tadahiro Kuroda (ICIP, 2009)

A versatile recognition processor employing Haar-like feature and cascaded classifier. - Yuya Hanai; Yuichi Hori; Jun Nishimura; Tadahiro Kuroda (ISSCC, 2009)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. - Yasufumi Sugimori; Yoshinori Kohama; Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2009)

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Tadahiro Kuroda; Masayuki Mizuno (ISSCC, 2009)

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. - Vishal V. Kulkarni; Muhammad Muqsith; Kiichi Niitsu; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

A High-Speed Inductive-Coupling Link With Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

Architecture Design of Versatile Recognition Processor for Sensornet Applications. - Yuichi Hori; Yuya Hanai; Jun Nishimura; Tadahiro Kuroda (IEEE Micro, 2009)

A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. - Lechang Liu; Makoto Takamiya; Tsuyoshi Sekitani; Yoshiaki Noguchi; Shintaro Nakano; Koichiro Zaitsu; Tadahiro Kuroda; Takao Someya; Takayasu Sakurai (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A versatile recognition processor for sensor network applications. - Risako Takashima; Yuya Hanai; Yuichi Hori; Tadahiro Kuroda (ASP-DAC, 2010)

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. - Keita Takatsu; Hirotaka Tamura; Takuji Yamamoto; Yoshiyasu Doi; Kouichi Kanda; Takayuki Shibasaki; Tadahiro Kuroda (CICC, 2010)

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. - Tsutomu Takeya; Kazuhisa Sunaga; Koichi Yamaguchi; Hideyuki Sugita; Yoichi Yoshida; Masayuki Mizuno; Tadahiro Kuroda (CICC, 2010)

A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. - Shusuke Kawai; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2010)

An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. - Noriyuki Miura; Kazutaka Kasuga; Mitsuko Saito; Tadahiro Kuroda (ISSCC, 2010)

A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. - Mitsuko Saito; Noriyuki Miura; Tadahiro Kuroda (ISSCC, 2010)

Wireless proximity interfaces with a pulse-based inductive coupling technique. - Hiroki Ishikuro; Tadahiro Kuroda (IEEE Commun. Mag., 2010)

A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS. - Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. - Yanfei Chen; Xiaolei Zhu 002; Hirotaka Tamura; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Junji Ogawa; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme. - Vishal V. Kulkarni; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link. - Yuxiang Yuan; Yoichi Yoshida; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. - Xiaolei Zhu 002; Yanfei Chen; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Hirotaka Tamura; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Masayuki Mizuno; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yoshinori Kohama; Yasufumi Sugimori; Kazutaka Kasuga; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2010)

1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. - Kazutoshi Tomita; Ryota Shinoda; Tadahiro Kuroda; Hiroki Ishikuro (A-SSCC, 2011)

A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. - Won-Joo Yun; Hiroki Ishikuro; Tadahiro Kuroda (A-SSCC, 2011)

A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. - Ryota Sekimoto; Akira Shikata; Tadahiro Kuroda; Hiroki Ishikuro (ESSCIRC, 2011)

A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. - Noriyuki Miura; Yasuhiro Take; Mitsuko Saito; Yoichi Yoshida; Tadahiro Kuroda (ISSCC, 2011)

6W/25mm2 inductive power transfer for non-contact wafer-level testing. - Andrzej Radecki; Hayun Chung; Yoichi Yoshida; Noriyuki Miura; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2011)

A 12Gb/s non-contact interface with coupled transmission lines. - Tsutomu Takeya; Lan Nan; Shinya Nakano; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2011)

A vertical bubble flow network using inductive-coupling for 3-D CMPs. - Hiroki Matsutani; Yasuhiro Take; Daisuke Sasaki; Masayuki Kimura; Yuki Ono; Yukinori Nishiyama; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (NOCS, 2011)

ThruChip interface (TCI) for 3D networks on chip. - Tadahiro Kuroda (VLSI-SoC, 2011)

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range. - Keita Takatsu; Hirotaka Tamura; Takuji Yamamoto; Yoshiyasu Doi; Kouichi Kanda; Takayuki Shibasaki; Tadahiro Kuroda (IEICE Trans. Electron., 2011)

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. - Noriyuki Miura; Tsunaaki Shidei; Yuxiang Yuan; Shusuke Kawai; Keita Takatsu; Yuji Kiyota; Yuichi Asano; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2011)

A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface. - Yasuhiro Take; Noriyuki Miura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2011)

A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. - Kiichi Niitsu; Vishwesh V. Kulkarni; Shinmo Kang; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yasufumi Sugimori; Yoshinori Kohama; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)

3-D NoC on Inductive Wireless Interconnect. - Hiroki Matsutani; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (3D Integration for NoC-based SoC Architectures, 2011)

Vertical Link On/Off Control Methods for Wireless 3-D NoCs. - Hao Zhang 020; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (ARCS, 2012)

Simultaneous data and power transmission using nested clover coils. - Yasuhiro Take; Hayun Chung; Noriyuki Miura; Tadahiro Kuroda (ASP-DAC, 2012)

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. - Atsutake Kosuge; Wataru Mizuhara; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2012)

A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. - Lechang Liu; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2012)

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. - Yasuhisa Shimazaki; Noriyuki Miura; Tadahiro Kuroda (COOL Chips, 2012)

An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ESSCIRC, 2012)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Eiichi Sasaki; Hideharu Amano; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2012)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Hideharu Amano; Hiroki Matsutani; Noriyuki Miura; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPT, 2012)

A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. - Takayuki Abe; Yuxiang Yuan; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee. - Tadahiro Kuroda; David Ruffieux (ISSCC, 2012)

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. - Won-Joo Yun; Shinya Nakano; Wataru Mizuhara; Atsutake Kosuge; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. - Takeshi Matsubara; Isamu Hayashi; Abul Hasan Johari; Tadahiro Kuroda; Hiroki Ishikuro (RWS, 2012)

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. - Xiaolei Zhu 002; Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda (VLSI-DAT, 2012)

A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM. - Noriyuki Miura; Mitsuko Saito; Tadahiro Kuroda (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing. - Andrzej Radecki; Hayun Chung; Yoichi Yoshida; Noriyuki Miura; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2012)

A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration. - Xiaolei Zhu 002; Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2012)

A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. - Hayun Chung; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. - Hayun Chung; Andrzej Radecki; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. - Andrzej Radecki; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. - Andrzej Radecki; Yuxiang Yuan; Noriyuki Miura; Iori Aikawa; Yasuhiro Take; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. - Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2012)

1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. - Kazutoshi Tomita; Ryota Shinoda; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2012)

A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. - Kiichi Niitsu; Shusuke Kawai; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A case for wireless 3D NoCs for CMPs. - Hiroki Matsutani; Paul Bogdan; Radu Marculescu; Yasuhiro Take; Daisuke Sasaki; Hao Zhang 020; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (ASP-DAC, 2013)

A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ASP-DAC, 2013)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. - Yusuke Koizumi; Noriyuki Miura; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2013)

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. - Noriyuki Miura; Yusuke Koizumi; Eiichi Sasaki; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (Hot Chips Symposium, 2013)

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. - Katsuki Ohata; Yukitoshi Sanada; Tetsuro Ogaki; Kento Matsuyama; Takanori Ohira; Satoshi Chikuda; Masaki Igarashi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Tadahiro Kuroda (ICECS, 2013)

Adaptive window search using semantic texton forests for real-time object detection. - Yuki Ono; Abdul Raziz Junaidi; Tadahiro Kuroda (ICIP, 2013)

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. - Yuki Urano; Won-Joo Yun; Tadahiro Kuroda; Hiroki Ishikuro (ISCAS, 2013)

F3: Emerging technologies for wireline communication. - Elad Alon; Azita Emami; Gerrit den Besten; Ichiro Fujimori; Tadahiro Kuroda; Masafumi Nogawa; Hisakatsu Yamaguchi (ISSCC, 2013)

Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillator. - Haruki Fukuda; Takahide Terada; Tadahiro Kuroda (ISSCC, 2013)

A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. - Noriyuki Miura; Mitsuko Saito; Masao Taguchi; Tadahiro Kuroda (ISSCC, 2013)

A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. - Wataru Mizuhara; Tsunaaki Shidei; Atsutake Kosuge; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

3D clock distribution using vertically/horizontally-coupled resonators. - Yasuhiro Take; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA. - Teruo Jyo; Tadahiro Kuroda; Hiroki Ishikuro (RWS, 2013)

An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. - Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEICE Trans. Electron., 2013)

A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. - Akira Shikata; Ryota Sekimoto; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Symbol-Rate Clock Recovery for Integrating DFE Receivers. - Tsutomu Takeya; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications. - Tsutomu Takeya; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. - Hao Zhang 020; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (IEICE Trans. Inf. Syst., 2013)

A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. - Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2013)

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. - Tsutomu Takeya; Lan Nan; Shinya Nakano; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2013)

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. - Noriyuki Miura; Yusuke Koizumi; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (IEEE Micro, 2013)

An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ASP-DAC, 2014)

Low-latency wireless 3D NoCs via randomized shortcut chips. - Hiroki Matsutani; Michihiro Koibuchi; Ikki Fujiwara; Takahiro Kagami; Yasuhiro Take; Tadahiro Kuroda; Paul Bogdan; Radu Marculescu; Hideharu Amano (DATE, 2014)

30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. - Atsutake Kosuge; Shu Ishizuka; Lechang Liu; Akira Okada; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2014)

F2: 3D stacking technologies for image sensors and memories. - Yusuke Oike; Makoto Ikeda; Albert Theuwissen; Johannes Solhusvik; Jonathan Chang; Tadahiro Kuroda (ISSCC, 2014)

A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. - Abdul Raziz Junaidi; Yasuhiro Take; Tadahiro Kuroda (VLSIC, 2014)

Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage. - Lechang Liu; Keisuke Ishikawa; Tadahiro Kuroda (IEICE Trans. Electron., 2014)

Wearable sensor-based human activity recognition from environmental background sounds. - Yi Zhan; Tadahiro Kuroda (J. Ambient Intell. Humaniz. Comput., 2014)

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. - Timothy C. Fischer; Byeong-Gyu Nam; Leland Chang; Tadahiro Kuroda; Michiel A. P. Pertijs (IEEE J. Solid State Circuits, 2014)

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. - Atsutake Kosuge; Wataru Mizuhara; Tsunaaki Shidei; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2014)

3D NoC with Inductive-Coupling Links for Building-Block SiPs. - Yasuhiro Take; Hiroki Matsutani; Daisuke Sasaki; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Computers, 2014)

Design and analysis for ThruChip design for manufacturing (DFM). - Li-Chung Hsu; Yasuhiro Take; Atsutake Kosuge; So Hasegawa; Junichiro Kadamoto; Tadahiro Kuroda (ASP-DAC, 2015)

Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. - Akira Okada; Abdul Raziz Junaidi; Yasuhiro Take; Atsutake Kosuge; Tadahiro Kuroda (ASP-DAC, 2015)

24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%. - Atsutake Kosuge; Shu Ishizuka; Marni Abe; Satoshi Ichikawa; Tadahiro Kuroda (ISSCC, 2015)

10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. - Atsutake Kosuge; Shu Ishizuka; Junichiro Kadomoto; Tadahiro Kuroda (ISSCC, 2015)

Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. - Masayuki Ikebe; Daisuke Uchida; Yasuhiro Take; Makito Someya; Satoshi Chikuda; Kento Matsuyama; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (VLSIC, 2015)

Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (VLSIC, 2015)

A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. - Li-Chung Hsu; Junichiro Kadomoto; So Hasegawa; Atsutake Kosuge; Yasuhiro Take; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. - Li-Chung Hsu; Masato Motomura; Yasuhiro Take; Tadahiro Kuroda (IEICE Trans. Electron., 2015)

Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network. - Yasuhiro Take; Tadahiro Kuroda (IEICE Trans. Electron., 2015)

Transponder Array System with Universal On-Sheet Reference Scheme for Wireless Mobile Sensor Networks without Battery or Oscillator. - Takahide Terada; Haruki Fukuda; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. - Kamal El-Sankary; Tetsuya Asai; Masato Motomura; Tadahiro Kuroda (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. - Atsutake Kosuge; Shu Ishizuka; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Analytical thruchip inductive coupling channel design optimization. - Li-Chung Hsu; Junichiro Kadomoto; So Hasegawa; Atsutake Kosuge; Yasuhiro Take; Tadahiro Kuroda (ASP-DAC, 2016)

An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. - Junichiro Kadomoto; Tomoki Miyata; Hideharu Amano; Tadahiro Kuroda (A-SSCC, 2016)

Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. - Tetsuya Asai; Masafumi Mori; Toshiyuki Itou; Yasuhiro Take; Masayuki Ikebe; Tadahiro Kuroda; Masato Motomura (ESSCIRC, 2016)

A 1 Tb/s/mm2 inductive-coupling side-by-side chip link. - So Hasegawa; Junichiro Kadomoto; Atsutake Kosuge; Tadahiro Kuroda (ESSCIRC, 2016)

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. - Akio Nomura; Hiroki Matsutani; Tadahiro Kuroda; Junichiro Kadomoto; Yusuke Matsushita 001; Hideharu Amano (CANDAR, 2016)

Deep learning application trial to lung cancer diagnosis for medical sensor systems. - Ryota Shimizu; Shusuke Yanagawa; Yasutaka Monde; Hiroki Yamagishi; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISOCC, 2016)

Low-energy algorithm for self-controlled Wireless Sensor Nodes. - Ahmad Muzaffar bin Baharudin; Mika Saari; Pekka Sillberg; Petri Rantanen; Jari Soini; Tadahiro Kuroda (WINCOM, 2016)

Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO. - Junichiro Kadomoto; So Hasegawa; Yusuke Kiuchi; Atsutake Kosuge; Tadahiro Kuroda (IEICE Trans. Electron., 2016)

An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver. - Atsutake Kosuge; Junichiro Kadomoto; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2016)

A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. - Atsutake Kosuge; Akira Okada; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An image sensor/processor 3D stacked module featuring ThruChip interfaces. - Masayuki Ikebe; Tetsuya Asai; Masafumi Mori; Toshiyuki Itou; Daisuke Uchida; Yasuhiro Take; Tadahiro Kuroda; Masato Motomura (ASP-DAC, 2017)

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. - Akio Nomura; Junichiro Kadomoto; Tadahiro Kuroda; Hideharu Amano (CANDAR, 2017)

Building block multi-chip systems using inductive coupling through chip interface. - Hideharu Amano; Tadahiro Kuroda; Hiroshi Nakamura; Kimiyoshi Usami; Masaaki Kondo; Hiroki Matsutani; Mitaro Namiki (ISOCC, 2017)

An inductive-coupling link for 3-D Network-on-Chips. - Junichiro Kadomoto; Hideharu Amano; Tadahiro Kuroda (ISOCC, 2017)

Convolutional neural network for industrial egg classification. - Ryota Shimizu; Shusuke Yanagawa; Toru Shimizu; Mototsugu Hamada; Tadahiro Kuroda (ISOCC, 2017)

Wireless power transfer to stacked modules for IoT sensor nodes. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISOCC, 2017)

Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network. - Ryota Shimizu; Kosuke Asako; Hiroki Ojima; Shohei Morinaga; Mototsugu Hamada; Tadahiro Kuroda (AI4I, 2018)

Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISCAS, 2018)

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Junichiro Kadomoto; Tomoki Miyata; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (ISSCC, 2018)

Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation. - Tsuyoshi Maruyama; Mototsugu Hamada; Tadahiro Kuroda (MWSCAS, 2018)

Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Tadahiro Kuroda (MWSCAS, 2018)

Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. - Yuta Toeda; Takumi Fujimaki; Mototsugu Hamada; Tadahiro Kuroda (VLSI Circuits, 2018)

Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (IEICE Trans. Electron., 2018)

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. - Akio Nomura; Yusuke Matsushita 001; Junichiro Kadomoto; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano (Int. J. Netw. Comput., 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. - Tomoya Arakawa; Joshin Sone; Mitsuji Okada; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2019)

Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. - Takahisa Tanaka; K. Tabuchi; Kohei Tatehora; Yohsuke Shiiki; S. Nakagawa; Tsunaki Takahashi; R. Shimizu; Hiroki Ishikuro; Tadahiro Kuroda; T. Yanagida; Ken Uchida (VLSI Circuits, 2019)

Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter. - Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Electron., 2019)

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2019)

A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. - Kohei Ando; Kazuhisa Akatsuka; Chaoran Cheng; Tomoya Arakawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ICECS, 2020)

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2020)

Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. - Tatsuo Omori; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2021)

A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. - Kota Shiba; Tatsuo Omori; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2021)

A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. - Saito Shibata; Reiji Miura; Yoshiki Sawabe; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (A-SSCC, 2021)

CA2 area detection from hippocampal microscope images using deep learning. - Shohei Morinaga; Tomoe Ishikawa; Masato Yasui; Mototsugu Hamada; Tadahiro Kuroda (MWSCAS, 2021)

A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. - Reiji Miura; Saito Shibata; Masahiro Usui; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2022)

A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. - Yao-Chung Hsu; Atsutake Kosuge; Rei Sumikawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. - Saito Shibata; Yoshiki Sawabe; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ICECS 2022, 2022)

A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. - Ximing Wang; Atsutake Kosuge; Yasuhiro Hayashi; Mototsugu Hamada; Tadahiro Kuroda (ICECS 2022, 2022)

Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2022)

An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. - Lixing Yu; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (SAS, 2022)

A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2022)

A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. - Atsutake Kosuge; Yao-Chung Hsu; Mototsugu Hamada; Tadahiro Kuroda (IEEE Open J. Circuits Syst., 2022)

Proximity Wireless Communication Technologies: An Overview and Design Guidelines. - Atsutake Kosuge; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. - Atsutake Kosuge; Satoshi Suehiro; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Instrum. Meas., 2022)

A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. - Yao-Chung Hsu; Atsutake Kosuge; Rei Sumikawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2023)

A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. - Rei Sumikawa; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2023)

An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. - Eitaro Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IECON, 2023)

A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. - Dongzhu Li; Yao-Chung Hsu; Rei Sumikawa; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2023)

Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. - Ximing Wang; Atsutake Kosuge; Yasuhiro Hayashi; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2023)

A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. - Atsutake Kosuge; Rei Sumikawa; Yao-Chung Hsu; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (VLSI Technology and Circuits, 2023)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2023)

A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. - Atsutake Kosuge; Yao-Chung Hsu; Rei Sumikawa; Mototsugu Hamada; Tadahiro Kuroda; Tomoe Ishikawa (IEEE Micro, 2023)

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. - Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Electron., 2023)

Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. - Dongzhu Li; Tianqi Zhao; Kenji Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2024)

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. - Dongzhu Li; Zhijie Zhan; Rei Sumikawa; Mototsugu Hamada; Atsutake Kosuge; Tadahiro Kuroda (IEICE Trans. Electron., 2024)

Slashing IC Power and Democratizing IC Access for the Digital Age. - Tadahiro Kuroda (IPSJ Trans. Syst. LSI Des. Methodol., 2024)

Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. - Atsutake Kosuge; Hirofumi Sumi; Naonobu Shimamoto; Yukinori Ochiai; Yurie Inoue; Hideharu Amano; Tohru Mogami; Yoshio Mita; Makoto Ikeda; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2025)